3D Semiconductor Lead-Out Contact Region Segmentation
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Solution Overview
Problem
The increasing complexity of multilayer laminated structures in 3D semiconductor device manufacturing leads to significant time consumption and manufacturing costs due to the multiplication of processing steps, with photoresist damage and pattern distortion issues, resulting in reduced memory integration density and increased risk of short circuits or open circuits.
Innovation Solution
The method involves dividing the lead-out contact region into sub-partitions and performing selective etching in each sub-partition using a photoresist mask, reducing the total number of etching steps and improving area utilization by slimming the photoresist and etching in different sub-partitions, allowing for efficient exposure of all material layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of dielectric layers is increased to improve device functionality, then the device complexity increases, but the time consumption and manufacturing cost grow significantly due to the multiplication of processing steps
Solution Approach 1:
The patent divides the lead-out contact region into multiple sub-partitions, each corresponding to different material layers. This segmentation allows parallel processing of different layers in different sub-partitions, reducing the total number of sequential processing steps while maintaining the functionality of multiple dielectric layers.
2Adaptability or versatility
If the number of dielectric layers is increased to improve device functionality, then the device complexity increases, but the manufacturing cost increases due to the multiplication of processing steps
Solution Approach 1:
The lead-out contact region is segmented into sub-partitions that can be processed independently and in parallel. This reduces the total number of sequential processing steps required, directly lowering manufacturing cost while supporting increased device functionality through multiple dielectric layers.
3Shape
If photoresist is repeatedly slimmed and re-coated to form stepped laminated structures, then the desired stepped structure is formed, but photoresist damage and pattern distortion occur
Solution Approach 1:
By segmenting the lead-out contact region into sub-partitions, the patent eliminates the need for repeated photoresist slimming and re-coating cycles. Each sub-partition can be processed independently with a single photoresist coating, preventing photoresist damage and pattern distortion while still forming the required stepped laminated structure.
4Shape
If repeated photoresist slimming and stair-etching processes are used to form stepped structures, then the stepped laminated structure is formed, but the area utilization of the lead-out contact region decreases
Solution Approach 1:
The lead-out contact region is divided into sub-partitions that are processed in parallel, eliminating the need for extensive lateral etching required in traditional stepped structures. This segmentation approach maintains better area utilization by reducing the lateral space consumed by the lead-out contact region while still achieving the necessary stepped configuration for multiple dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach dramatically reduces the total number of etching process steps and enhances the area utilization of the lead-out contact region, improving the integration density and reliability of three-dimensional semiconductor devices by minimizing distortion and waste.
Implementation Method 1
forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed in said plurality of sub-partitions
Implementation Method 2
After forming the widest stair at the bottom via RIE etching the laminated structure
Implementation Method 3
using the processes of UV lighting, laser irradiation, heating or chemical treatment to slim the photoresist
Implementation Method 4
using the processes of UV lighting, laser irradiation, heating or chemical treatment to slim the photoresist
Implementation Method 5
using the processes of UV lighting, laser irradiation, heating or chemical treatment to slim the photoresist
Implementation Method 6
using the processes of UV lighting, laser irradiation, heating or chemical treatment to slim the photoresist
Data Source
AI summary
A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said steps d and step e, until all of the second material layers are exposed; g) forming contact leads, connecting each of the plurality of the second material layers. In accordance with the method of the present invention, the total number of etching process steps is reduced dramatically and the area utilization is improved effectively by selectively etching each of the sub-partitions.