Semiconductor Contact Pitch Optimization via Regional Segmentation

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Solution Overview

Problem

Semiconductor devices face challenges in achieving high integration and miniaturization due to limitations in forming components of reduced size at desired positions, which affects their reliability and functionality.

Innovation Solution

A semiconductor device with a cell region and a core region, featuring active regions, interlayer insulating layers, upper and lower contacts, and dummy contacts, where the contacts are arranged in specific patterns to ensure electrical connectivity and insulation, allowing for improved integration and reliability by optimizing contact pitch and shape.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If components are reduced in size and disposed at desired positions to achieve high integration and miniaturization, then device integration and compactness are improved, but manufacturing difficulty increases due to restrictions on facilities and processes

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing difficulty
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent applies local quality by differentiating contact formation processes between cell regions and core regions. Different contact pitches and contact patterns are used in different regions of the semiconductor device, allowing optimization for high integration in cell regions while maintaining manufacturability in core regions. This regional differentiation resolves the contradiction by enabling miniaturization where needed without compromising overall manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the contact formation process into multiple stages with different pitch requirements. First contacts are formed at a first pitch in cell regions and a second pitch in core regions, then second contacts are formed at a third pitch that differs from the first pitch. This segmentation allows the device to achieve high integration through reduced pitch in specific regions while maintaining manufacturing capability through the use of multiple fabrication steps.

Inventive Principle:
Principle #1Segmentation

2Productivity

If contact pitch is reduced to increase integration density, then device integration is improved, but contact formation precision and reliability deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidcontact formation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs dynamic pitch adjustment where the contact pitch varies by region and by contact layer. First contacts have a first pitch in cell regions and a second pitch in core regions, while second contacts have a third pitch that is greater than the first pitch. This dynamic variation in pitch allows high integration density in cell regions with first contacts while ensuring manufacturing precision for second contacts with larger spacing, thus resolving the contradiction between integration density and formation precision.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent resolves the pitch precision contradiction by transitioning to another dimension - using vertical stacking of contact layers. Instead of attempting to form all contacts at a single reduced pitch, the invention uses multiple contact layers (first contacts and second contacts) with different pitches in the vertical dimension. This allows the device to achieve high integration through layered architecture while maintaining precision by forming each contact layer at an appropriate pitch for its specific manufacturing requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8741767B2Method of forming semiconductor device
Publication Date: 2014.06.03 SAMSUNG ELECTRONICS CO LTD
  • US8741767B2 patent drawing
  • US8741767B2 patent drawing
  • US8741767B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.