Semiconductor Contact Structure Layout for Lower DRAM Contact Resistance
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Solution Overview
Problem
The reduction in size of semiconductor devices, particularly in the core region of DRAMs, leads to increased contact resistance due to design rule limitations, which affects the performance of the semiconductor structure.
Innovation Solution
A semiconductor structure design with first and second contact structures having larger top surfaces than bottom surfaces, and third contact structures with interfaces, along with an adhesive layer to enhance conductivity and connection strength, reducing resistance and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the contact size in the core region is reduced according to design rules, then the device size is reduced, but the contact resistance increases
Solution Approach 1:
The contact structure is divided into multiple segments: a first contact structure with a first contact hole, a second contact structure with a second contact hole, and a third contact structure with a third contact hole. These contact structures are arranged at different positions and depths, creating a segmented pathway for current flow that bypasses the limitation of reduced contact area at any single location.
Solution Approach 2:
The patent transitions from a two-dimensional contact area reduction to a three-dimensional contact network. By stacking contact structures at different vertical levels (different z-heights) and horizontal positions, the invention creates a multi-dimensional conductive pathway that maintains low resistance even when individual contact areas are minimized according to design rules.
2Productivity
If the device size is reduced to increase integration, then the contact area is reduced, but the conductivity decreases
Solution Approach 1:
The contact structures are nested within the semiconductor device architecture, with contact holes formed through different layers at different vertical levels. The first, second, and third contact structures are positioned at different heights and can be nested within or adjacent to each other, creating a compact three-dimensional arrangement that maintains high conductivity within a small footprint.
Solution Approach 2:
The patent employs composite contact structures that may include different materials for different contact holes or contact regions. This allows optimization of electrical properties in different parts of the contact network, maintaining high conductivity despite reduced overall device size and contact area.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a base, first contact structures, second contact structure, and third contact structures. The base includes an active region, and a source region, a gate region, and a drain region that are sequentially adjacent to each other are formed in the active region; the first contact structures are provided on the source region and the drain region; the second contact structure is provided on the gate region; the third contact structures are provided on first contact structures and the second contact structure, an area of a top surface of the first contact structure and an area of a top surface of the second contact structure are both larger than an area of a bottom surface of the third contact structure.