Semiconductor Device Contact Resistance via Pre-Amorphization Implantation
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Solution Overview
Problem
As semiconductor devices shrink in size, contact resistance between the source contact/drain contact and the source junction/drain junction becomes significant, posing a challenge for improving electrical performance and reducing resistance in semiconductor manufacturing processes.
Innovation Solution
A pre-amorphization implantation (PAI) process is performed to form an amorphous region in the epitaxial layer after forming specific openings, ensuring the amorphous region is not influenced by subsequent processes, thereby reducing contact resistance through the formation of alloy layers and silicide regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is continuously shrunk to increase functional device density, then the number and density of functional devices in each chip region are improved, but contact resistance between source contact/drain contact and source junction/drain junction increases significantly
Solution Approach 1:
The patent applies preliminary action by performing the pre-amorphization implantation (PAI) process before forming the source contact and drain contact. The PAI process creates an amorphous region in the epitaxial layer that is subsequently recrystallized to form a low-resistance contact region. This preliminary preparation of the contact region reduces contact resistance before the actual contact formation, enabling continued device scaling without compromising electrical performance
2Reliability
If PAI process is performed before forming the second opening (gate structure opening), then contact resistance reduction is achieved, but the amorphous region is influenced by subsequent processing steps which may compromise its integrity
Solution Approach 1:
The patent performs the PAI process and forms the amorphous region as a preliminary step before forming the second opening through the gate structure. This timing ensures that the amorphous region is created and stabilized before subsequent processing steps that involve the gate structure, preventing the amorphous region from being influenced or damaged by these later processes
Solution Approach 2:
The patent segments the manufacturing process into distinct sequential steps: first forming the amorphous region via PAI, then forming the second opening through the gate structure. This segmentation isolates the amorphous region formation from subsequent gate structure processing, protecting the amorphous region's integrity while still achieving contact resistance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PAI process effectively lowers contact resistance by forming amorphous regions that are protected from subsequent processing steps, enhancing the electrical performance of semiconductor devices by maintaining the integrity of the amorphous regions and ensuring efficient recrystallization.
Implementation Method 1
a pre-amorphization implantation (PAI) process is performed for forming an amorphous region in the epitaxial layer
Implementation Method 2
forming an amorphous region in the epitaxial layer after a first opening and a second opening are sequentially formed
Data Source
AI summary
A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.