Semiconductor Contact Resistance Reduction via Pre-Amorphous Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High contact resistance at the silicide/semiconductor substrate interface in semiconductor devices due to implantation-induced defects and interface roughness, which affects device yield and reliability.
Innovation Solution
A method involving pre-amorphous implantation to eliminate defects and neutral species implantation to adjust the work function and doping concentration, followed by silicide formation, to reduce contact resistance. This includes steps like pre-amorphization implantation to create amorphous regions and neutral species implantation to improve the silicide/doped region interface, along with annealing and native oxide removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If implantation processes are used to dope the semiconductor substrate, then the doping concentration is improved, but implantation-induced defects increase causing higher contact resistance
Solution Approach 1:
A pre-amorphization implantation step is performed before the main doping implantation. This preliminary action creates an amorphous layer that absorbs implantation damage, preventing defects from forming in the crystal lattice during subsequent doping processes, thereby reducing contact resistance while maintaining doping concentration
Solution Approach 2:
An amorphous silicon layer is introduced as an intermediary between the implantation process and the crystal lattice. This amorphous layer acts as a buffer that captures implantation-induced defects, preventing them from interacting with the silicide and causing junction leakage, thus reducing contact resistance
2Device complexity
If the silicide/semiconductor interface is formed directly after implantation, then the fabrication process is simplified, but interface roughness increases causing higher contact resistance
Solution Approach 1:
An annealing process is performed before silicide formation to repair implantation-induced damage and smooth the interface. This preliminary thermal treatment reduces interface roughness and eliminates defects, enabling low contact resistance without adding significant fabrication complexity
Solution Approach 2:
The interface quality is improved by changing the physical state of the material through annealing. The thermal energy supplied during annealing enables atomic rearrangement that smooths the interface and repairs defects, thereby reducing contact resistance while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces contact resistance by eliminating junction leakage and improving the interfacial resistance, leading to enhanced semiconductor device performance and reliability.
Implementation Method 1
performing a pre-amorphous implantation over the doped region of the substrate
Implementation Method 2
performing a neutral species implantation over the doped region of the substrate
Implementation Method 3
performing an annealing process, such as a rapid thermal process (RTP), to activate the doped region(s)
Data Source
AI summary
A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped region(s) of the semiconductor substrate. Subsequently, a silicide is formed in the doped region(s). By conducting a pre-amorphous implantation combined with a neutral species implantation, the present invention reduces the contact resistance, such as at the contact area silicide and source/drain substrate interface.