Semiconductor Contact Fabrication Reducing Resistance and Bridge Defects

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Solution Overview

Problem

Highly integrated semiconductor devices, such as DRAM devices, face increased contact resistance and bridge defects due to reduced contact areas and integration levels, which affect their performance and reliability.

Innovation Solution

A method for fabricating semiconductor devices involving the formation of a device isolation layer pattern on a substrate to create isolated active regions, followed by the deposition of insulating and conductive layers, and the use of a mask pattern to etch and form pillar-shaped structures and openings that allow for the creation of wiring structures with reduced contact resistance and minimized bridge defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integration degree is increased, then the device density is improved, but the contact area is decreased and contact resistance is increased

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure is divided into multiple segments: a lower contact portion extending into the active region and an upper contact portion at the surface, connected by a conductive filler. This segmentation allows the contact to maintain electrical connectivity while adapting to the reduced contact area in highly integrated devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact structure employs a nested configuration where the lower contact portion is embedded within the active region, the conductive filler is nested within the contact hole, and the upper contact portion is positioned at the surface. This nested arrangement maximizes the use of limited space while maintaining effective electrical connection.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If the integration degree is increased, then the device density is improved, but bridge defects between contact and adjacent patterns increase

Engineering Contradiction:
Improvedevice densityVSAvoidbridge defects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure has different properties at different locations: the lower contact portion has a larger cross-sectional area for mechanical stability and low resistance, the conductive filler provides electrical connectivity through the insulating layer, and the upper contact portion connects to surface patterns. This local differentiation reduces bridge defects by ensuring each portion is optimized for its specific function.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The conductive filler acts as an intermediary element that bridges the lower contact portion and the upper contact portion, ensuring electrical connectivity while being isolated from adjacent patterns by the insulating layer. This intermediary structure prevents unwanted electrical interaction with neighboring patterns, reducing bridge defects.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the fabrication of semiconductor devices with reduced contact resistance and decreased bridge defects, resulting in improved performance and reliability of highly integrated semiconductor devices like DRAM devices.

Implementation Method 1

the mask pattern may be formed as a photoresist pattern through a photo process

Methodology Applied
Scientific EffectPhoto process: Photography

Implementation Method 2

The first conductive layer and the insulating layer are etched to expose the active region of the first contact forming region by using the mask pattern

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS9159730B2Methods for fabricating a semiconductor device
Publication Date: 2015.10.13 SAMSUNG ELECTRONICS CO LTD
  • US9159730B2 patent drawing
  • US9159730B2 patent drawing
  • US9159730B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.