3D Contact Structure Reducing Resistance in Semiconductor Devices
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Solution Overview
Problem
In highly integrated semiconductor memory devices, transistors with horizontal channel regions face issues such as increased leakage current, decreased breakdown voltage, and elevated current due to short channel effects, and the contact resistance between metal contacts and impurity regions becomes a challenge as the integration level increases, leading to difficulties in maintaining low resistance and structural stability.
Innovation Solution
A semiconductor device with a contact structure that surrounds the impurity region in three dimensions, formed using polysilicon doped with impurities, which increases the contact area and reduces resistance, and is manufactured through a self-alignment process within an insulation interlayer to ensure precise positioning and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact area between the impurity region and the contact is decreased due to increased integration, then the device density is increased, but the contact resistance between the contact and the impurity region is increased
Solution Approach 1:
The patent transitions from a two-dimensional contact interface to a three-dimensional contact structure by forming the contact in a hole that extends through multiple layers. This vertical dimension allows the contact to maintain adequate contact area with the impurity region even as horizontal dimensions are reduced for higher integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-dimensional contact structure effectively decreases contact resistance and enhances the electrical properties and reliability of the semiconductor device by increasing the contact area and preventing misalignment issues, thereby addressing the limitations of traditional contact structures in high-integration devices.
Implementation Method 1
the contact structure effectively decreases contact resistance and enhances the electrical properties
Implementation Method 2
formed through a self-alignment process within an insulation interlayer to ensure precise positioning
Data Source
AI summary
In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.