Semiconductor Contact Pattern With Rising And Recessed Portions
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Solution Overview
Problem
As the integration of semiconductor devices increases, parasitic capacitance between gate and contact patterns becomes significant, making it challenging to reduce the thickness of gate patterns and width of contact patterns due to increased resistance.
Innovation Solution
The semiconductor device incorporates a contact pattern with a rising portion and a recessed portion, where the recessed portion is lower than the rising portion, and includes an insulating pattern and a via pattern, to reduce parasitic capacitance by optimizing the layout and structure of the contact and gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of gate pattern is reduced to reduce parasitic capacitance, then parasitic capacitance decreases, but resistance of gate pattern increases
Solution Approach 1:
The contact pattern transitions from a two-dimensional planar structure to a three-dimensional structure with rising portions extending upward. This vertical dimension allows the contact pattern to maintain electrical connection while reducing horizontal overlap area with the gate pattern, thereby reducing parasitic capacitance without increasing resistance.
Solution Approach 2:
The recessed portion of the contact pattern is positioned within the projection area of the gate pattern, creating a nested spatial relationship. This arrangement minimizes the overlapping area between the gate pattern and contact pattern, reducing parasitic capacitance while maintaining effective electrical connection through the rising portions.
2Object-affected harmful factors
If the width of contact pattern is reduced to reduce parasitic capacitance, then parasitic capacitance decreases, but resistance of contact pattern increases
Solution Approach 1:
The contact pattern utilizes vertical extension through rising portions to maintain electrical connection effectiveness without requiring increased horizontal width. This three-dimensional approach reduces the horizontal footprint and overlapping area with gate patterns, thereby reducing parasitic capacitance while maintaining low resistance through the vertical conductive path.
3Adaptability or versatility
If integration degree increases, then device functionality improves, but parasitic capacitance between gate and contact patterns increases
Solution Approach 1:
The contact pattern is segmented into multiple functional regions: recessed portions that minimize overlap with gate patterns, and rising portions that provide vertical electrical connection. This segmentation allows the contact pattern to fulfill multiple functions while reducing parasitic capacitance through optimized spatial arrangement.
Solution Approach 2:
Different portions of the contact pattern have different spatial characteristics: recessed portions are positioned to minimize overlap with gate patterns (low capacitance region), while rising portions extend upward to ensure good electrical connection (low resistance region). This local differentiation optimizes both capacitance and resistance characteristics simultaneously.
Data Source
AI summary
Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion.