Semiconductor Contact Structure With Rough Metal Liner for Lower Resistance
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Solution Overview
Problem
As semiconductor devices integrate more functionality and increase in performance, the smaller size of transistors and wirings leads to higher resistance and capacitance, making high-speed operation challenging due to increased resistance and capacitance between wirings.
Innovation Solution
The semiconductor device incorporates a metal liner with surface roughness on the contact structures, including a PVD-formed tungsten layer, to reduce resistance and enhance adhesion, replacing traditional barrier metals like Ti/TiN, and uses selective deposition processes for metal layers to improve contact plug structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of wirings is decreased to achieve higher integration, then the degree of integration is improved, but the resistance of the wirings increases
Solution Approach 1:
The patent changes the material parameter of the wiring from conventional metal to conductive polymer, which has different electrical resistance characteristics. This allows maintaining lower resistance even at reduced wiring dimensions, thus resolving the contradiction between higher integration and increased resistance.
Solution Approach 2:
The patent employs composite structures including conductive polymer layers combined with metal electrodes and interlayer insulating materials. This composite approach enables optimized electrical properties that balance integration density and resistance characteristics.
2Productivity
If the size of wirings is decreased to achieve higher integration, then the degree of integration is improved, but the capacitance between wirings increases
Solution Approach 1:
The patent introduces low-dielectric constant interlayer insulating materials and adjusts the physical parameters of wiring structures (width, thickness, spacing) to reduce parasitic capacitance. This enables higher integration while controlling capacitance between closely spaced wirings.
Solution Approach 2:
The patent applies different material properties and structural configurations to different regions of the wiring system. Conductive polymer layers are used in specific high-capacitance regions, while metal electrodes are used in other areas, optimizing the local electrical characteristics to minimize overall capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical characteristics by reducing resistance and improving adhesion, enabling better high-speed operation and integration in semiconductor devices.
Implementation Method 1
an external surface of the metal liner has surface roughness
Implementation Method 2
a PVD-formed tungsten layer
Data Source
AI summary
A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.