Semiconductor Contact Structure with Sacrificial Spacer Groove
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Solution Overview
Problem
Traditional approaches to semiconductor device manufacturing face challenges in achieving low resistance and high speed while ensuring reliability and reproducibility, particularly due to trade-offs between feature size, operation speed, and reliability.
Innovation Solution
A semiconductor device with a contact structure comprising a device isolation pattern, gate pattern, doped regions, gate spacers, interlayer dielectric, and sacrificial spacers, where the sacrificial spacers have etch selectivity, allowing for the formation of grooves to create contact structures that reduce resistance and enhance operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional manufacturing approaches are used to minimize feature size, then device integration density increases, but operation speed and reliability deteriorate due to increased resistance
Solution Approach 1:
The contact structure is divided into multiple segments: a contact hole portion extending vertically from the substrate, and a contact line portion extending laterally from the contact hole. This segmentation allows the contact to reach the active region at optimal depths while maintaining low resistance pathways, resolving the contradiction between high integration density and reliable operation.
Solution Approach 2:
The contact structure transitions from a traditional vertical contact hole to a three-dimensional structure that includes both vertical (contact hole) and lateral (contact line) dimensions. This dimensional expansion enables the contact to access the active region effectively while providing extended conductive pathways that reduce resistance without increasing footprint area.
2Quantity of substance
If feature size is decreased to increase integration density, then more devices fit on the substrate, but manufacturing precision and reproducibility become difficult to maintain
Solution Approach 1:
The gate spacer is formed first as a reference structure before forming the contact structure. The contact line portion is then formed to extend from the contact hole to a predetermined distance from the gate spacer. This preliminary action establishes precise geometric references that guide subsequent manufacturing steps, maintaining precision even as feature sizes decrease for higher integration density.
Solution Approach 2:
The gate spacer serves as an intermediary reference structure that mediates the positioning and dimensional control of the contact structure. By using the gate spacer as a geometric reference, the manufacturing process can achieve precise contact line placement and width control without directly measuring from the shrinking active region dimensions.
3Area of moving object
If contact structure dimensions are reduced to maintain scaling, then device area decreases, but resistance increases and turn-on current decreases
Solution Approach 1:
The contact structure utilizes both vertical depth (contact hole) and lateral extension (contact line) to provide extended conductive pathways. This three-dimensional configuration increases the effective contact area and conductive volume without proportionally increasing the surface footprint, thereby maintaining low resistance and high turn-on current while preserving scaling benefits.
Solution Approach 2:
The contact structure employs composite material stacking, including the interlayer dielectric layer and the conductive contact material, to optimize electrical performance. The combination of insulating dielectric materials and conductive contact materials creates a structure that provides both electrical connectivity and proper isolation, achieving low resistance without compromising device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of semiconductor devices with optimized contact structures that reduce resistance, increase turn-on current, and improve reproducibility, addressing the limitations of traditional manufacturing methods.
Implementation Method 1
a sacrificial spacer interposed between the interlayer dielectric and the gate spacer disposed on the device isolation pattern, the sacrificial spacer including an insulating material having an etch selectivity with respect to the gate spacer and the interlayer dielectric
Data Source
AI summary
An approach is provided for semiconductor devices and methods for providing a contact structure. Methods may include forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the active region and being disposed on the device isolation pattern, and forming a first doped region and a second doped region in the active region adjacent to opposite sides of the gate pattern, respectively. The methods may include sequentially forming a gate spacer and a sacrificial spacer on both sidewalls of the gate pattern, forming an interlayer dielectric on the entire surface of the substrate, planarizing the interlayer dielectric to expose the gate spacer and the sacrificial spacer, removing a portion of the sacrificial spacer to form a groove to expose the first doped region, and forming a contact structure in the groove.