3D Semiconductor Contact Structure for Scaled MOSFET Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to negative impacts on operational properties, necessitating advancements in integration density and electrical characteristics.
Innovation Solution
A three-dimensional semiconductor device is designed with stacked transistors and specific patterning of channel and source/drain regions, along with strategically placed contacts and gate electrodes, to enhance integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then pattern size is reduced, but operational properties of the semiconductor device deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOS-FETs to three-dimensional vertically stacked transistors. Multiple active regions (first active region, second active region, third active region) are stacked vertically along the third direction, enabling increased integration density while maintaining operational properties through improved electrical characteristics of the vertical structure
Solution Approach 2:
The semiconductor device is divided into multiple discrete active regions (first, second, and third active regions) that are vertically segmented. Each active region contains channel patterns and source/drain patterns that can be independently optimized, allowing the device to achieve both small footprint and reliable operation through modular architecture
2Productivity
If conventional two-dimensional MOS-FET layout is used, then manufacturing is simpler, but integration density is insufficient
Solution Approach 1:
The patent employs vertical stacking of multiple active regions along the third direction to achieve three-dimensional integration. This dimensional transition dramatically increases integration density by utilizing the vertical space above each substrate region, accommodating multiple transistors and interconnect layers within a compact footprint
Solution Approach 2:
The device structure implements nested arrangements where second active regions are positioned above first active regions, and third active regions are positioned above second active regions. This nested vertical configuration allows multiple functional layers to be integrated within a compact volume, significantly enhancing integration density
3Productivity
If vertically stacked transistors are implemented, then integration density is increased, but contact structure complexity increases
Solution Approach 1:
The contact structure is segmented into multiple distinct components: lower contacts extending in the first direction, first active contacts coupled to lower contacts, and second active contacts coupled to upper source/drain patterns. This segmentation allows each contact element to be independently formed and optimized, managing the complexity of electrical connections in the vertically stacked architecture
Solution Approach 2:
The contact structure utilizes vertical dimensionality with lower contacts positioned in the first active region and upper contacts positioned in the second active region. This vertical separation of contact functions enables independent formation processes and reduces lateral interference, managing contact complexity through three-dimensional spatial arrangement
Data Source
AI summary
A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.