Semiconductor Contact Formation via Composite Spacer Alignment
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Solution Overview
Problem
Conventional methods for forming contacts in semiconductor devices, particularly for DRAM structures with critical dimensions less than 20 nanometers, are complex, costly, and prone to issues like contact resistance and short circuits due to the difficulty in aligning and forming three-dimensional contacts.
Innovation Solution
A method involving the formation of contact holes extending into semiconductive pillars with composite structures of oxide and nitride materials, where conductive plugs are filled within these holes, and nitride spacers are used to align and separate the contacts, reducing processing complexity and cost while enhancing feature density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form 3D contacts for DRAM device structures with critical dimensions less than 20 nm, then contact resistance can be decreased through increased contact surface area, but the manufacturing process becomes complex and costly with alignment difficulties
Solution Approach 1:
The patent divides the contact formation process into distinct segments: first forming digit line contacts in initial contact holes, then forming storage node contacts in subsequent contact holes. This segmentation allows each contact type to be formed with optimized processes and alignment requirements, reducing overall manufacturing complexity while maintaining low contact resistance through proper 3D contact geometry
Solution Approach 2:
The patent performs preliminary actions by forming the digit line contacts and their associated structures before forming the storage node contacts. This preliminary formation establishes a stable foundation and reference structure that simplifies subsequent alignment processes, reducing manufacturing complexity while ensuring proper 3D contact geometry for low resistance
2Reliability
If conventional methods are used to form 3D contacts, then contact surface area can be increased to decrease contact resistance, but alignment precision deteriorates leading to potential short circuits
Solution Approach 1:
The patent uses intermediary structures such as mandrels, spacers, and caps that are formed between the digit line and storage node contact formation steps. These intermediaries serve as alignment references and physical guides that ensure precise positioning of storage node contacts relative to digit line contacts, maintaining manufacturing precision while enabling the 3D contact geometry needed for low resistance
Solution Approach 2:
The contact formation process is segmented into distinct stages with intermediate structures formed between stages. This segmentation allows each contact type to be aligned independently using appropriate intermediary structures, maintaining high precision for each contact while achieving the overall 3D contact architecture required for low contact resistance
3Shape
If conventional dry etching processes are used to form 3D contacts, then contact geometry can be achieved, but material loss occurs requiring thicker nitride caps and increased feature dimensions
Solution Approach 1:
The patent applies beforehand cushioning by forming thicker mandrel structures and adjusting spacer dimensions to compensate for the material loss that will occur during subsequent dry etching processes. This preliminary over-compensation ensures that after etching, the final contact geometry achieves the desired 3D shape with adequate nitride cap thickness and proper feature dimensions, maintaining both contact geometry and material integrity
Data Source
AI summary
A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars. Semiconductor device structures and additional methods are also described.