Semiconductor Contact Formation via Sidewall Spacer Segmentation
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Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges in forming contacts due to optical proximity effects and defects such as voids in the dielectric layer, which lead to issues like short circuits and parasitic resistances, especially when etching contact holes with a high aspect ratio.
Innovation Solution
A method is developed to form electrically isolated gates and contacts by cutting gate lines and conductive sidewall spacers using reactive ion etching or laser cutting, eliminating the need for traditional contact hole etching and allowing self-aligned sidewall spacers to serve as contacts, thereby simplifying the contact formation process and preventing defects like voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional contact hole etching is used to form contacts on gates and sources/drains, then contacts can be formed to both regions, but the etching depth varies causing shorts between gate and contact hole or under-etching with voids in filled metals
Solution Approach 1:
The contact formation process is segmented into two separate stages: first forming gate sidewall spacers that define gate contact regions, then forming source/drain sidewall spacers that define source/drain contact regions. This segmentation allows each contact type to be formed with appropriate etching depth control independent of the other, eliminating the short circuit and under-etching problems caused by single-stage etching with varying depths.
2Manufacturing precision
If sidewall spacer material is deposited after cuts are formed in gate patterns, then gate patterns are defined, but spacer material enters inside the cuts causing sidewall spacers of adjacent gates to merge and creating voids in the dielectric layer
Solution Approach 1:
The gate sidewall spacers are formed preliminarily before the final cutting of gate patterns. The spacer material is deposited conformally on the gate structures, and then the gate patterns are cut through the spacers. This preliminary formation ensures that the spacers are properly defined and positioned before cutting, preventing material from entering cuts and merging adjacent spacers, thereby eliminating voids and defects in the dielectric layer.
3Productivity
If photolithography resolution is pushed to form smaller features, then circuit density increases, but optical proximity effects cause serious image distortions
Solution Approach 1:
The patterning process is segmented into multiple exposure and development steps rather than attempting to form all features in a single photolithography step. This multi-step segmentation approach allows each exposure to focus on specific pattern elements with optimized parameters, reducing optical proximity effects and image distortions while achieving high circuit density through cumulative pattern formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the contact formation process, reduces parasitic resistances, and ensures accurate electrical isolation between devices, improving the overall quality and reliability of semiconductor devices by eliminating voids and ensuring flush surfaces for adjacent transistors and contacts.
Implementation Method 1
cutting gate lines and conductive sidewall spacers using reactive ion etching or laser cutting
Implementation Method 2
cutting gate lines and conductive sidewall spacers using reactive ion etching or laser cutting
Data Source
AI summary
A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.