Semiconductor Contact Structure Layout for Stress-Relieved 3D Stacks
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Solution Overview
Problem
The manufacturing of high-density semiconductor devices, such as 3D NAND flash memory, faces challenges with stress issues causing conductive layer bending and loss of high-K dielectric material, leading to breakdown voltage problems and non-uniform structure, which affects the reliability and quality of the device.
Innovation Solution
The semiconductor device incorporates a contact structure design with a first conductive layer offsetting along a horizontal direction, protected by adjacent isolating layers, and a bottom layer with a thicker center, reducing the need for thicker isolating layers and allowing controlled filling material placement, while also separating gate line structures into segments to alleviate stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device uses high-K dielectric material in conductive layers, then memory density and storage capacity are improved, but stress issues cause conductive layer bending and loss of dielectric material leading to breakdown voltage problems
Solution Approach 1:
The conductive layer is segmented into multiple portions along the vertical direction, with isolating layers positioned between adjacent conductive layers. This segmentation prevents stress-induced bending and dielectric material loss by electrically and physically separating the conductive portions, thereby maintaining breakdown voltage reliability while preserving high memory density
Solution Approach 2:
The isolating layers are selectively positioned at specific locations between conductive layers where stress concentration occurs. This local quality approach targets the problematic regions with enhanced isolation structures, preventing dielectric material loss and bending at critical points while maintaining overall device performance
2Quantity of substance
If the device stacks more layers within similar footprint to increase density, then memory cell density is improved, but stress issues and non-uniform structure worsen affecting reliability
Solution Approach 1:
By dividing the stacked structure into segmented conductive layers separated by isolating layers, the patent maintains structural uniformity despite increased stacking density. The isolating layers act as stress-relief interfaces that prevent cumulative stress from compromising the overall structural stability of the high-density stack
Solution Approach 2:
The isolating layers serve as intermediary structures between adjacent conductive layers in the stack. These intermediaries buffer mechanical stress and prevent stress transfer between layers, thereby maintaining structural uniformity and reliability in high-density stacked configurations
3Reliability
If the device uses thicker isolating layers to prevent dielectric material loss, then breakdown voltage reliability is improved, but device size increases and manufacturing complexity worsens
Solution Approach 1:
Rather than uniformly increasing isolating layer thickness throughout the device, the patent applies thicker or enhanced isolating structures only at specific locations where stress concentration and dielectric material loss are most problematic. This localized approach maintains breakdown voltage reliability while minimizing overall device size and manufacturing complexity
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing contact structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers alternating with each other along a first direction and a second stack of dielectric layers and isolating layers alternating with each other along the first direction. A connection region of the semiconductor device is adjacent to an array region of the semiconductor device in a second direction perpendicular to the first direction. The second stack is in the connection region and is connected to the first stack. The semiconductor device further includes contact structures extending through at least a part of the second stack along the first direction.