Semiconductor Contact Structure for Reduced Resistance and Etching Damage
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Solution Overview
Problem
Existing semiconductor device manufacturing techniques face challenges with increasing contact resistance and miniaturization, particularly due to groove-shaped contact portions that complicate wire design, lead to increased wire resistance and capacitance, and pose risks of etching damage and shorting.
Innovation Solution
The semiconductor device features groove-shaped first contact portions connected to source/drain regions and hole-shaped second contact portions on a shared interlayer insulating layer, allowing for flexible wire design and simultaneous etching without damaging the gate electrode, while applying tensile or compression stress to improve carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If groove-shaped contact portions are used to reduce contact resistance, then contact resistance decreases, but wire design freedom is reduced and wire resistance/capacitance increase
Solution Approach 1:
The contact structure is divided into two segments: groove-shaped first contact portions connected to source/drain regions, and hole-shaped second contact portions on the gate electrode. This segmentation allows each contact type to serve its specific function independently, resolving the conflict between contact resistance reduction and wire design freedom.
Solution Approach 2:
The invention transitions from a single-plane contact structure to a multi-layered contact structure with contacts at different vertical levels. The groove-shaped first contact portions are in the lower interlayer insulating layer, while hole-shaped second contact portions are in the upper interlayer insulating layer, enabling three-dimensional wire routing and improving design freedom.
2Reliability
If groove-shaped contact portions are formed by etching, then contact resistance decreases, but etching damage to gate electrode increases
Solution Approach 1:
The etching process is segmented into two separate operations: forming groove-shaped first contact portions in the lower interlayer insulating layer, and forming hole-shaped second contact portions in the upper interlayer insulating layer. This segmentation allows controlled etching depth for each contact type, preventing over-etching damage to the gate electrode.
Solution Approach 2:
The groove-shaped first contact portions are formed in advance in the lower interlayer insulating layer before forming the hole-shaped second contact portions in the upper layer. This preliminary action establishes the first contact structure with appropriate etching depth, preventing subsequent etching damage to the gate electrode when forming the second contact portions.
3Area of stationary object
If circuit miniaturization is implemented, then device area decreases, but shorting between contact portions increases
Solution Approach 1:
The invention utilizes vertical dimension by placing groove-shaped first contact portions in the lower interlayer insulating layer and hole-shaped second contact portions in the upper interlayer insulating layer. This three-dimensional arrangement increases spatial separation between contacts, reducing shorting risk even as circuit area is reduced through miniaturization.
Solution Approach 2:
The groove-shaped first contact portions are formed in advance with proper depth control in the lower interlayer insulating layer, establishing a foundation that prevents shorting before the upper layer contacts are formed. This preliminary structuring ensures adequate isolation is maintained during subsequent miniaturization processes.
4Productivity
If different etching depths are used for gate electrode and source/drain regions, then contact portions can be formed simultaneously, but gate electrode damage increases
Solution Approach 1:
The contact formation process is segmented into two independent stages: forming groove-shaped first contact portions in the lower interlayer insulating layer, and forming hole-shaped second contact portions in the upper interlayer insulating layer. This segmentation allows each etching operation to use optimized depth parameters specific to its target layer, preventing gate electrode damage while maintaining productivity.
Solution Approach 2:
The groove-shaped first contact portions are formed in advance in the lower interlayer insulating layer with controlled etching depth that stops before reaching the gate electrode. This preliminary formation establishes the first contact structure safely, enabling subsequent formation of second contact portions without risking gate electrode damage.
Data Source
AI summary
A method for manufacturing a semiconductor device includes the steps of: (a) forming a gate electrode on a substrate, forming source/drain regions and a channel forming region in the substrate, and forming on the source/drain regions a first interlayer insulating layer equal in height to the gate electrode; (b) forming in the first interlayer insulating layer groove-shaped first contact portions connected to the source/drain regions; (c) forming a second interlayer insulating layer on a whole surface; (d) forming hole-shaped second contact portions in portions of the second interlayer insulating layer on the first contact portion; and (e) forming on the second interlayer insulating layer wires connected to the second contact portions.