Semiconductor Contact Studs for Reduced Gate Capacitance
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Solution Overview
Problem
As semiconductor devices shrink in size, the increasing density of circuit elements leads to undesired interactions, such as parasitic capacitance and gate-to-source/drain coupling, which degrade performance.
Innovation Solution
The solution involves placing source and drain contact studs on the opposite side of the substrate from the gate structure, increasing the physical distance between the gate and source/drain contacts while maintaining the same lateral dimensions, thereby reducing capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If contact stubs and trenches are placed closer to the gate structure to increase circuit density, then device density is improved, but parasitic capacitance and gate-to-source/drain coupling increase degrading performance
Solution Approach 1:
The patent applies dimensionality change by moving the source and drain contact studs from the same side of the substrate as the gate structure to the opposite side. This spatial reconfiguration in the vertical dimension increases the physical distance between the gate and source/drain contacts, thereby reducing parasitic capacitance and gate-to-source/drain coupling while maintaining high circuit density on the surface.
2Quantity of substance
If contact stubs and trenches are placed closer to the gate structure to increase circuit density, then device density is improved, but gate-to-source/drain coupling increases degrading performance
Solution Approach 1:
The patent resolves the contradiction between density and reliability by utilizing the vertical dimension through substrate thickness. By placing contact studs on the opposite side of the substrate from the gate structure, it achieves both high circuit density on the surface and reduced parasitic coupling, thereby maintaining device performance.
3Reliability
If the physical distance between gate and source/drain contacts is increased to reduce parasitic capacitance, then performance is improved, but device density decreases
Solution Approach 1:
The patent reconciles the trade-off between performance and density by exploiting the third dimension (substrate depth). The gate structure remains on the surface for high density, while source and drain contacts are positioned on the opposite side of the substrate, achieving both close lateral spacing for density and large vertical separation for reduced parasitic effects.
Data Source
AI summary
A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate.