Semiconductor Package Contact Traces with Segmented Plating
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in producing robust IC packages with a greater number of leads or solder bumps in a smaller and thinner form factor, leading to issues such as plated contacts peeling away due to increased density and thinner plating requirements.
Innovation Solution
The development of a semiconductor package with contact traces plated on a metal substrate, where support structures are integrated to absorb heat and stress during mounting, providing structural support and reducing peeling, while maintaining a thin profile and minimizing additional manufacturing steps or costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of contacts or leads is increased to achieve more I/O in a smaller package, then the number of input/output connections is improved, but the plated contacts become less robust and more prone to peeling away
Solution Approach 1:
The contact structure is segmented into multiple functional layers: a thick plating layer (10-20 micrometers) for mechanical strength and stress resistance, a thinner functional plating layer (0.5-5 micrometers) for electrical conductivity and solderability, and an optional intermediate layer for adhesion enhancement. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between contact density and robustness.
Solution Approach 2:
The patent employs composite plating structures combining different metal materials with complementary properties. For example, a copper base layer provides mechanical strength and stress resistance, while outer layers of nickel, palladium, or gold provide corrosion resistance, electrical conductivity, and solderability. This composite approach enables thin overall package design while maintaining contact robustness through material property optimization.
2Length of moving object
If the package thickness is reduced to achieve a thinner form factor, then the compactness is improved, but the plated contacts become more susceptible to peeling due to reduced structural support
Solution Approach 1:
The patent applies local quality enhancement by concentrating plating thickness and material strength at critical locations where peeling stress occurs, such as the interface between the contact and the substrate. The thick plating layer (10-20 micrometers) is strategically positioned at these stress concentration points, while thinner regions are used where mechanical stress is minimal. This localized reinforcement maintains reliability without increasing overall package thickness.
Solution Approach 2:
The patent implements preliminary reinforcement measures by applying multiple plating layers and adhesion-promoting intermediate layers before the final package assembly. These preliminary structural preparations ensure that the contact traces have inherent resistance to peeling stresses that will occur during subsequent mounting and operation, preventing reliability issues before they manifest.
3Manufacturing precision
If numerous processing steps are used to fabricate semiconductor packages with high contact density, then the manufacturing precision is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple plating operations into integrated processing sequences. For example, the base plating, intermediate adhesion layers, and functional plating layers are deposited in a coordinated multi-step process that can be performed in a single plating line setup, reducing the number of separate processing cycles. This merging approach maintains the precision required for high contact density while simplifying the overall manufacturing workflow.
Solution Approach 2:
The plating process is designed to serve multiple functions simultaneously: establishing electrical conductivity, providing mechanical strength, ensuring adhesion to the substrate, and enabling subsequent soldering operations. By making the plating system universal and multi-functional, the patent reduces the need for separate specialized processing steps, thereby decreasing device complexity while maintaining manufacturing precision for high-density contact arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of semiconductor packages with a thickness of fractions of a millimeter, offering improved robustness and reliability by reducing the occurrence of contact traces peeling away, while maintaining a small form factor and cost-effectiveness.
Implementation Method 1
The contact traces are plated onto a metal substrate, such as copper, and when the substrate is sacrificed, what are left are the contact traces
Implementation Method 2
The support structures serve to absorb heat during the process of mounting the package to an end application
Implementation Method 3
The support structures serve to absorb heat during the process of mounting the package to an end application, absorbing stress applied to the contact
Data Source
AI summary
A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.