Semiconductor Contact Triple Dot Zigzag Arrangement
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Solution Overview
Problem
In semiconductor devices like NAND type flash memory, miniaturization and integration lead to challenges in reducing contact size and spacing without causing short-circuiting, lowering breakdown voltage, or increasing contact resistance, especially with traditional zigzag arrangements.
Innovation Solution
A triple dot zigzag arrangement of contacts is implemented with specific positioning and double development techniques to reduce contact spacing below the resolution limit, maintaining chip surface area and preventing short-circuiting while maintaining breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional zigzag arrangement of contacts is used, then manufacturing process is simple, but contact spacing cannot be reduced below resolution limit
Solution Approach 1:
The contact arrangement is segmented into multiple groups (first group with contacts at positions A1, A2, A3 and second group with contacts at positions B1, B2, B3) that are offset from each other. This segmentation allows each group to be formed with sufficient spacing while achieving overall higher contact density through the offset arrangement, resolving the contradiction between reduced contact spacing and manufacturing precision.
Solution Approach 2:
The invention transitions from a single-row zigzag arrangement to a multi-row offset arrangement where contacts are distributed across different positions (A1-A3 and B1-B3) with offsets in both horizontal and vertical directions. This dimensional expansion allows contact spacing to be reduced in one direction while maintaining adequate spacing in other directions, overcoming the resolution limit constraint.
2Quantity of substance
If contact size is reduced to increase arrangement density, then contact spacing decreases, but short-circuiting risk increases
Solution Approach 1:
Contacts are segmented into multiple groups positioned at different locations (A1, A2, A3 and B1, B2, B3) with deliberate offsets between groups. This segmentation maintains adequate spacing between contact groups while allowing higher density within each group, increasing overall arrangement density without causing short-circuits between adjacent contacts.
Solution Approach 2:
The contact arrangement uses asymmetric offset positions where the second group of contacts (B1, B2, B3) is offset by different distances in horizontal direction (D1, D2, D3) and vertical direction (E1, E2, E3) relative to the first group. This asymmetric arrangement optimizes spacing to prevent short-circuits while maximizing contact density.
3Quantity of substance
If contact spacing is reduced below resolution limit, then arrangement density increases, but manufacturing precision deteriorates
Solution Approach 1:
The invention resolves the resolution limit constraint by distributing contacts across multiple rows with offsets in both horizontal and vertical dimensions. Contacts in different rows (A1-A3 and B1-B3) can be positioned closer than the resolution limit in the horizontal direction while maintaining adequate vertical spacing, effectively bypassing the single-direction resolution constraint through multi-dimensional arrangement.
4Quantity of substance
If chip surface area is kept constant to reduce cost, then contact arrangement density must increase, but contact spacing becomes tighter
Solution Approach 1:
The contact array is segmented into multiple groups distributed across different positions on the chip surface. This segmentation allows contacts to be arranged in a pattern that maximizes density within the fixed chip area while maintaining adequate spacing between segmented groups, achieving higher contact density without proportionally reducing contact spacing.
Solution Approach 2:
By utilizing offsets in both horizontal and vertical dimensions, the invention effectively uses the two-dimensional chip surface more efficiently. Contacts are arranged in multiple rows with vertical offsets (E1, E2, E3) and horizontal offsets (D1, D2, D3), allowing higher contact density within the same chip area while maintaining adequate spacing through the multi-dimensional distribution pattern.
Data Source
AI summary
According to one embodiment, in a semiconductor device, a second contact is disposed at a position that is shifted from a first contact by a distance approximately of P in a first direction and by a distance approximately of √8×P in a second direction. A third contact is disposed at a position that is shifted from the first contact by a distance approximately of 2P in the first direction and by a distance approximately of √8×P/2 in the second direction. A fourth contact is disposed at a position that is shifted from the first contact by a distance approximately of 3P in the first direction. A fifth contact is disposed at a position that is shifted from the fourth contact by a distance approximately of P in the first direction and by a distance approximately of √8×P in the second direction.