Semiconductor Contact Hole Etching via Segmented Wall Portions
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Solution Overview
Problem
The existing technique for three-dimensionally arranging memory cells in semiconductor devices faces challenges in process controllability, particularly in controlling the depth of contact holes formed between conductive layers, which affects the etching process and can lead to difficulties in accurately connecting conductive layers to upper interconnects.
Innovation Solution
A semiconductor device with a stacked structure of conductive and insulating layers, where pairs of wall portions are formed with specific spacings to facilitate the formation of contact layers that connect conductive layers through open ends, allowing for controlled exposure and connection to contact electrodes, thereby improving process controllability and reducing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact holes are formed simultaneously and collectively for multiple conductive layers at different depths, then manufacturing efficiency is improved, but process controllability deteriorates due to difficulty in controlling the etching depth of each contact hole
Solution Approach 1:
The patent divides the contact formation process into separate stages for different conductive layers. Specifically, contact holes for lower conductive layers (e.g., first and second conductive layers) are formed at different times and with different etching conditions than contact holes for upper conductive layers (e.g., third and fourth conductive layers). This segmentation allows independent optimization and precise control of etching depth for each contact hole group, resolving the contradiction between simultaneous formation efficiency and depth control precision.
2Reliability
If conductive layers are connected through deep contact holes to upper interconnects, then electrical connection is achieved, but the risk of short circuits increases and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the contact hole formation into multiple batches corresponding to different conductive layers. Contact holes penetrating through insulating layers to reach specific conductive layers are formed in separate etching processes, allowing precise control of each contact hole's depth and termination point. This prevents short circuits between adjacent conductive layers while ensuring reliable electrical connections.
Solution Approach 2:
The patent performs preliminary formation of contact holes for lower conductive layers before forming contact holes for upper conductive layers. By establishing the depth and positioning of lower contact holes first, subsequent etching processes for upper contact holes can be precisely controlled to avoid overlapping or shorting, thereby maintaining manufacturing precision while achieving reliable electrical connections.
Data Source
AI summary
A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.