Semiconductor Context Switching Circuit Segmentation

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Solution Overview

Problem

As the number of contexts increases in semiconductor devices, the circuit size expands, leading to increased memory requirements and decreased circuit performance due to the need to update all data sets during context switching, even when only partial data is changed.

Innovation Solution

A semiconductor device with a product-sum operation circuit comprising multiple operation circuits, switch circuits, and a controller that generates context signals to minimize the number of contexts switched, reducing the circuit size by allowing partial data updates and optimizing context switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of contexts is increased to support more circuit configurations, then the adaptability of the semiconductor device is improved, but the circuit size increases due to the need for additional memory sets

Engineering Contradiction:
Improvenumber of contextsVSAvoidcircuit size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent segments the context data into two distinct types: operation circuit data (first context) and switch circuit data (second context). Each type is stored in separate memory sets (first memory and second memory) and controlled by different context signals. This segmentation allows the system to manage multiple contexts without requiring a single large memory structure, thereby reducing the overall circuit size while maintaining high adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to context switching by creating two levels of context management: operation circuit contexts (first contexts) and switch circuit contexts (second contexts). This dimensional separation allows the system to handle complex configurations through coordinated switching at different levels, reducing the memory burden compared to a flat, single-level context structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If all data sets are updated during context switching to ensure consistency, then the reliability of the circuit is improved, but the operation speed decreases due to the time required to update all data

Engineering Contradiction:
Improvecircuit consistencyVSAvoidcontext switching speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By segmenting context data into operation circuit data and switch circuit data stored in separate memory sets, the patent enables independent updating of each segment. When context switching is required, only the specific memory set corresponding to the changed functionality needs to be updated, rather than forcing an update of all data sets. This segmentation maintains reliability by ensuring consistent state transitions while dramatically improving switching speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial action by allowing selective updating of only the necessary context data segments during switching operations. Instead of updating all data sets universally, the system updates only the first memory or second memory as needed, reducing the time required for context switching while maintaining circuit reliability through targeted consistency management.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If the circuit size is increased to accommodate more memory sets for multiple contexts, then the adaptability is improved, but the power consumption increases due to larger circuit components

Engineering Contradiction:
Improvenumber of contextsVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the context management system into segmented components with dedicated memory sets for different circuit elements. This segmentation prevents the need for a single large, power-hungry memory structure by distributing storage requirements across smaller, specialized memory sets. Each memory set can be independently managed and powered, reducing overall power consumption while supporting multiple contexts through coordinated switching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs partial action by activating and updating only the specific memory sets required for the current operational context. Instead of maintaining all context data in active, power-consuming states simultaneously, the patent selectively manages memory sets based on operational needs, reducing power consumption while preserving adaptability through on-demand context switching.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12190079B2Semiconductor device comprising operation circuits and a switch circuit
Publication Date: 2025.01.07 SEMICON ENERGY LAB CO LTD
  • US12190079B2 patent drawing
  • US12190079B2 patent drawing
  • US12190079B2 patent drawing

AI summary

A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.