Semiconductor Structure Coplanar Insulating Layers
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Solution Overview
Problem
In semiconductor fabrication, the difference in material levels between shallow trench isolation and active areas leads to a non-flat surface, increasing the risk of leakage and reducing device stability due to the need for conventional polishing techniques.
Innovation Solution
A semiconductor structure is formed with a substrate having an active area and a shallow trench isolation region, where a stacked structure is covered with multiple insulating layers, with the third insulating layer being polished to be coplanar with the first insulating layer on the active area, avoiding the need for conventional polishing that increases leakage risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional polishing is performed to provide a flat working surface, then the surface flatness is improved, but the mask layer thickness is reduced and leakage risk increases
Solution Approach 1:
The patent applies preliminary action by forming the stacked structure and first insulating layer conformally on the substrate before performing any planarization. This ensures that the mask layer is already in place and properly formed on the active areas before the polishing process begins, preventing thinning or removal of the mask layer during planarization. The conformal deposition is performed on the as-built substrate surface with height differences between STI and active areas, eliminating the need for subsequent mask layer polishing.
2Shape
If multiple planarization processes are performed to achieve flatness, then the surface flatness is improved, but the device complexity and process steps increase
Solution Approach 1:
The patent performs the conformal deposition of the stacked structure and first insulating layer as a preliminary action on the as-built substrate surface before any planarization is performed. This approach eliminates the need for multiple planarization processes by establishing the conformal structure in advance, thereby reducing process complexity while still achieving the required surface flatness for subsequent operations.
Solution Approach 2:
The patent applies local quality by allowing different regions of the substrate (active areas and STI regions) to have different heights and materials, and performing conformal deposition that adapts to these local variations. The conformal deposition process automatically adjusts to the local surface topology, forming uniform thickness layers regardless of the underlying height differences, thus eliminating the need for global planarization processes.
3Shape
If the mask layer is polished to thin it out for planarization, then the surface flatness is improved, but the working stability is reduced
Solution Approach 1:
The patent performs conformal deposition of the mask layer (first insulating layer) as a preliminary action on the as-built substrate surface before any planarization is performed. This ensures that the mask layer is already formed with sufficient thickness and proper coverage on the active areas before the polishing process begins, preventing thinning or removal of the mask layer during planarization and maintaining working stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a flat upper surface, reducing the risk of leakage and enhancing the stability of semiconductor devices by maintaining sufficient masking layer thickness and facilitating subsequent processes.
Implementation Method 1
sequentially depositing a stacked structure, a first insulating layer, a second insulating layer, and a third insulating layer
Implementation Method 2
polishing the third insulating layer with a first polishing rate, till exposing the second insulating layer disposed on the active area
Implementation Method 3
polishing the second insulating layer with a second polishing rate, till exposing the first insulating layer disposed on the active area, wherein the second polishing rate is different form the first polishing rate
Data Source
AI summary
A semiconductor structure, a fabricating method thereof and a semiconductor device, the structure includes a substrate having a STI region and an AA, with an upper surface of the STI region lower than an upper surface of the AA; a stacked covered on the substrate; a first insulating layer covered the stacked structure, a second insulating layer covered the first insulating layer, and a third insulating layer covered the second insulating layer, over the STI region; a first insulating layer covered the stacked structure, over the AA, with an upper surface of the first insulating layer coplanar with an upper surface of the third insulating layer. The structure provides a semiconductor structure having a flat upper surface, avoiding polishing the first insulating layer over the AA to level with the first insulating layer over the STI region, greatly increasing the leakage risk, and reducing working stability of semiconductor devices.