Semiconductor Device Low Resistance Inductance Copper Bumps
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving low electrical resistance and inductance while maintaining high reliability and cost-effectiveness, especially in high-power and high-speed applications, where traditional wire bonding methods are costly and prone to reliability issues, and flip-chip assembly methods are expensive and stressful.
Innovation Solution
A semiconductor device with a metallized active surface protected by an insulating overcoat, featuring copper-filled windows and a copper layer with copper bumps arranged in an alternating pattern, connected to elongated copper leads, which are soldered to a substrate and encapsulated for mechanical stability and low electrical noise, allowing for high current handling and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding assembly is used, then manufacturing cost is reduced, but electrical resistance and inductance increase
Solution Approach 1:
The patent merges the chip with the substrate by directly bonding the chip to the substrate without separate wire bonding interconnection steps. This integration eliminates the need for additional wire bonding materials and processes, reducing both manufacturing cost and parasitic inductance while maintaining electrical performance.
Solution Approach 2:
The patent extracts and eliminates the wire bonding interconnection layer from the system by implementing direct chip-to-substrate bonding. This removal of the wire bonding interface reduces parasitic inductance and resistance, improving electrical performance while simplifying the manufacturing process.
2Reliability
If solder ball flip-chip assembly is used, then electrical performance is improved, but manufacturing cost and reliability problems increase
Solution Approach 1:
The patent replaces expensive solder ball interconnections with a simpler, more cost-effective direct bonding approach using copper posts and conductive paste. This substitution eliminates the need for complex solder ball reflow processes and associated reliability issues while maintaining electrical performance.
Solution Approach 2:
The patent changes the bonding parameters from high-temperature solder ball reflow to lower-temperature direct copper bonding with conductive paste. This parameter change reduces manufacturing complexity and cost while improving reliability by eliminating solder joint stress and potential failure modes.
3Productivity
If higher integration is achieved, then device performance is improved, but feature size reduction increases difficulty of preserving clean signals
Solution Approach 1:
The patent transitions from planar signal routing to three-dimensional vertical interconnection through copper posts extending through the substrate. This dimensional change allows signals to bypass lateral interference paths while maintaining compact integration, preserving signal integrity despite reduced feature sizes and higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices to handle high currents with low electrical resistance and inductance, providing mechanical stability and reliability, even in accelerated stress tests, while reducing fabrication costs and silicon area usage.
Implementation Method 1
The copper layer has a thickness between about 10 and 15 μm, and the copper bumps have a height between about 30 and 70 μm. Devices according to the invention may be less than 1 mm thick; their low electrical resistance allows them to handle currents between 15 and 30 A
Implementation Method 2
The first surface of each lead is connecting the corresponding bumps of alternating lines, using solder elements
Data Source
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AI summary
A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces (110b) remain un-encapsulated. A copper heat slug (404) may be attached to chip surface (101b) using thermally conductive adhesive (403). Chip surface (101a), protected by an overcoat (103) has metallization traces (102). Copper-filled windows contact the traces and copper layers (105) parallel to traces. Copper bumps (108) are formed on each line in an orderly and repetitive arrangement so that the bumps of one line are positioned about midway between the bumps of the neighboring lines. A substrate has elongated leads (110) oriented at right angles to the lines; the leads connect the corresponding bumps of alternating lines.