Semiconductor Coprocessor Architecture for Sequential Sampling

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Solution Overview

Problem

Existing parallel GPU implementations are inefficient for accelerating sampling-based algorithms in probabilistic models due to the sequential nature of these algorithms, which prevents proper acceleration.

Innovation Solution

A dedicated processor-coprocessor architecture is utilized, where a precompiler distributes executable instructions between a processor and a coprocessor, with the coprocessor specializing in probability distribution calculations, enabling efficient execution of sampling-based algorithms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If parallel GPU implementations are used, then processing power is increased, but sampling-based algorithms cannot be properly accelerated due to their sequential nature

Engineering Contradiction:
Improveprocessing powerVSAvoidacceleration capability
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The system segments the probabilistic inference workload into distinct operational phases: sampling operations are executed on the coprocessor while other operations remain on the main processor. This segmentation allows the coprocessor to specialize in sampling tasks, achieving acceleration without forcing parallel execution on sequentially-dependent algorithms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A coprocessor is introduced as an intermediary specialized unit between the main processor and memory system. This coprocessor handles sampling-based algorithm execution, acting as a mediator that provides targeted acceleration for probabilistic inference tasks without requiring the main processor to execute these operations in parallel.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If multiple GPUs work in parallel, then computational capacity increases, but sampling-based algorithms still execute sequentially preventing acceleration

Engineering Contradiction:
Improvecomputational capacityVSAvoidexecution speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The coprocessor is designed with local quality specialized for sampling-based algorithms, featuring dedicated functional units and memory structures optimized for probabilistic inference. This localized specialization enables faster execution of sampling operations compared to general-purpose GPUs, achieving speed improvement through targeted hardware design rather than brute-force parallelization.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If general-purpose processors are used, then versatility is maintained, but specialized probability distribution calculations are inefficient

Engineering Contradiction:
Improveprocessing versatilityVSAvoidcalculation efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The coprocessor serves as a specialized intermediary that handles probability distribution calculations, freeing the main processor to maintain versatility for other tasks. This mediator approach allows the system to achieve both versatility (through the main processor) and calculation efficiency (through the coprocessor's specialized functionality).

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments computational tasks by function: the main processor handles general-purpose operations while the coprocessor handles specialized probability distribution calculations. This functional segmentation enables each unit to operate at optimal efficiency for its designated task type.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4565949B1Semiconductor systems and computer-implemented methods of probabilistic inference data processing
Publication Date: 2025.09.17 HAWAI TECH
  • EP4565949B1 patent drawingFigure 1~2
  • EP4565949B1 patent drawing
  • EP4565949B1 patent drawing

AI summary

The subject application provides a semiconductor system (100) and a computer-implemented method configured to provide probabilistic inference data processing for solving probabilistic model. The inventors have found that using a dedicated processor-coprocessor architecture enables the acceleration of sampling-based algorithms for solving probabilistic models. In particular, the inventors propose to configure a precompiler (150) that astutely distribute between a processor and a coprocessor (120), the executable instructions associated with portions of the computer program code (30) implementing the sampling-based algorithms. With the proposed architecture, the developer of a sampling-based algorithm does not have to explicitly code the drawing of random samples from probability distribution functions or part of a probabilistic fusion of probability distribution functions, since the corresponding executable instructions would be executed by the coprocessor (120) after a function call has been detected for the drawing of random samples from probability distribution functions or a probabilistic fusion.