Semiconductor Package Core Ball Structure for Warpage-Induced Bump Spacing
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Solution Overview
Problem
The increase in substrate area, asymmetrical chip arrangement, and weight of heat dissipation structures in semiconductor packages leads to warpage, increasing the likelihood of short circuits in external connection bumps.
Innovation Solution
A semiconductor package design featuring core balls with a core body and conductive material layer that partially surround and extend into the core body, with a width less than conductive bumps, and a through-hole structure to maintain spacing between bumps, reducing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the substrate area is increased to accommodate high-performance semiconductor chips, then the packaging capacity and performance are improved, but the warpage of the semiconductor package increases
Solution Approach 1:
The patent applies asymmetry by designing core balls with non-uniform width along their height direction. The width of the core ball varies from the first end to the second end, creating an asymmetric geometry that compensates for warpage effects. This asymmetric design allows the bump structure to better accommodate substrate deformation while maintaining electrical connectivity.
Solution Approach 2:
The patent changes the geometric parameters of the bumps by varying the width of core balls along their height. The width parameter transitions from a first width at the first end to a second width at the second end, allowing the bump structure to adapt to warpage conditions while maintaining structural integrity and electrical connection.
2Temperature
If heat dissipation structures with increased weight are added to improve thermal management, then the thermal performance is improved, but the warpage of the semiconductor package increases
Solution Approach 1:
The asymmetric width design of core balls compensates for warpage induced by heavy heat dissipation structures. The varying width along the height direction allows the bump to accommodate the additional weight and resulting deformation while maintaining reliable electrical connection.
3Adaptability or versatility
If asymmetrical arrangement of chip structures is implemented to optimize performance, then the functional performance is improved, but the warpage of the semiconductor package increases
Solution Approach 1:
The patent uses asymmetric core ball geometry to counterbalance the warpage effects caused by asymmetrical chip arrangements. The non-uniform width distribution in the core ball matches and compensates for the asymmetric stress distribution in the package.
4Reliability
If the width of external connection bumps is increased to improve electrical connectivity, then the connection reliability is improved, but the likelihood of short circuits between bumps increases
Solution Approach 1:
The asymmetric width design allows the bump to have adequate width for reliable connection at certain regions while maintaining sufficient spacing at other regions. The width varies from a first width to a second width along the height, optimizing both connectivity and short circuit prevention.
Solution Approach 2:
The patent resolves the spacing issue by utilizing the height dimension. Instead of uniformly increasing width in the horizontal plane, the width varies along the vertical height direction, allowing adequate horizontal spacing while maintaining connection reliability through the varied width profile.
Data Source
AI summary
A semiconductor package includes a substrate, at least one chip structure on a first surface of the substrate, connection bumps, an underfill layer that at least partially surrounds the connection bumps and is between the first surface of the substrate and the at least one chip structure, core balls, and conductive bumps on a second surface of the substrate, where respective ones of the core balls and respective ones of the conductive bumps are electrically connected to the respective ones of the lower pads, where each of the core balls includes a core body and a conductive material layer that at least partially surrounds and extends into the core body, and where a width of each of the core balls in a first direction is less than a width of each of the conductive bumps in the first direction.