Semiconductor Conductive Pillar Layout for Lower Core Resistance
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Solution Overview
Problem
As semiconductor technology advances and process nodes shrink, the high resistance of conductive pillars in the core area of semiconductor structures hinders the effective improvement of electrical performance.
Innovation Solution
A method for manufacturing a semiconductor structure involves forming a base with a lower dielectric layer and conductive pillars, where the third lower conductive pillar in the core area has a larger top surface area than the third upper conductive pillar, reducing resistance and improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the process node is shrunk to increase integration degree, then the function and cost performance are improved, but the resistance of conductive pillars increases
Solution Approach 1:
The patent applies local quality by differentiating the dimensions of conductive pillars based on their location. Core area conductive pillars have larger dimensions than peripheral area pillars, creating locally optimized electrical properties. This resolves the contradiction by allowing high integration degree overall while maintaining low resistance in the critical core area through localized dimensional enhancement.
2Reliability
If the dimension of conductive pillars is increased to reduce resistance, then the electrical performance is improved, but the area occupied by conductive structures increases
Solution Approach 1:
The patent implements local quality by making conductive pillars in the core area larger only where needed for low resistance, while keeping peripheral area pillars smaller. This localized dimensional differentiation reduces total area occupation while maintaining electrical performance in the critical core region, resolving the contradiction between resistance reduction and area conservation.
3Reliability
If the top surface area of lower conductive pillar is made larger than upper conductive pillar, then the resistance is reduced, but the manufacturing precision requirement increases
Solution Approach 1:
The patent applies preliminary action by forming the lower conductive pillar with larger dimensions first, before forming the upper conductive pillar. This sequential approach allows the larger lower pillar to be established as a foundation, with the upper pillar subsequently formed to match or be smaller than the lower pillar's top surface. This preliminary sizing resolves the contradiction by enabling resistance reduction through larger dimensions while managing manufacturing precision through a controlled formation sequence.
Data Source
AI summary
A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a base; forming a lower dielectric layer; forming a first lower conductive pillar located in an array area, a second lower conductive pillar located in a peripheral area and a third lower conductive pillar located in a core area; forming an upper dielectric layer that exposes top surfaces of the first lower conductive pillar, the second lower conductive pillar and the third lower conductive pillar; and forming a first upper conductive pillar, a second upper conductive pillar and a third upper conductive pillar that are located within the upper dielectric layer; in which the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar, and a top surface area of the third lower conductive pillar is larger than a top surface area of the third upper conductive pillar.