Semiconductor Core Region Voltage Fluctuation Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, particularly System On Chip (SOC) technology, there is a challenge in reducing voltage fluctuations and power consumption due to significant voltage drops across wires supplying power and reference potentials to functional blocks, which affects the reliability and efficiency of the device.
Innovation Solution
The solution involves a semiconductor device design where power supply pads and reference pads are strategically placed within the core region, with power switches integrated to reduce wiring resistance and voltage drops, allowing for independent power management of functional blocks, thereby minimizing voltage fluctuations and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power supply pads and reference pads are placed in the I/O region (conventional design), then the core region can be maximized for functional blocks, but voltage drops across wires become significant and affect reliability
Solution Approach 1:
The semiconductor chip is divided into distinct regions: I/O region for input/output circuits, core region for functional blocks, and a dedicated pad region for power supply and reference pads. This segmentation allows optimal placement of pads near the core region to minimize wire lengths and voltage drops, while maintaining sufficient core region area for functional blocks.
Solution Approach 2:
A dedicated pad region acts as an intermediary zone between the I/O region and core region. Power supply pads and reference pads are placed in this intermediate area, serving as mediators that reduce the distance for power delivery to functional blocks while not encroaching significantly on the core region area.
2Reliability
If wire lengths are shortened to reduce voltage drops, then voltage stability improves, but the layout complexity and design difficulty increase
Solution Approach 1:
By segmenting the chip into distinct regions (I/O region, core region, pad region), the layout of power supply networks becomes more systematic and less complex. The pad region serves as a centralized hub for power distribution, making routing easier to manage compared to dispersed pad placements.
Solution Approach 2:
Multiple reference pads are strategically placed in the pad region to create equipotential zones near the core region. This approach stabilizes reference potential across the chip without requiring excessively long reference wires, simplifying the layout while maintaining voltage stability.
3Reliability
If power switches are integrated close to functional blocks, then voltage drops are reduced, but the area available for functional blocks decreases
Solution Approach 1:
Power switches are placed in the pad region, which acts as an intermediary zone between the power supply pads and the core region containing functional blocks. This positioning allows power switches to be close enough to functional blocks to minimize voltage drops, while the pad region itself does not significantly reduce the area available for functional blocks.
4Reliability
If multiple reference pads are placed throughout the chip, then voltage fluctuations are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple reference pads are concentrated in the dedicated pad region rather than being dispersed throughout the entire chip. This segmented approach maintains voltage stability benefits while simplifying the manufacturing process by localizing the additional structures to a specific region, making the overall fabrication process more manageable.
Data Source
AI summary
A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.