Semiconductor Counter Circuit with Adjustable Clock Division for Latency Management
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Solution Overview
Problem
Synchronous semiconductor memory devices, such as DDR3-SDRAM, face challenges in managing a wide range of latencies due to the need for numerous flip-flops and increased power consumption, especially during high-speed operations, which results in a large circuit scale and high charge/discharge currents.
Innovation Solution
A semiconductor device with a clock generating circuit that produces two divided clocks with adjustable phases, allowing for flexible control of latency counting through a shift register, enabling precise latency management without increasing the number of stages and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If many flip-flops are implemented to count a wide range of latencies, then the latency counting capability is improved, but the circuit scale and consumption current increase
Solution Approach 1:
The patent applies dynamics by making the clock division ratio adjustable rather than fixed. The clock generating circuit can dynamically change the division ratio based on the required latency value, allowing a single shift register to adapt to different latency requirements. This resolves the contradiction by enabling wide latency range coverage without requiring separate hardware for each latency value.
Solution Approach 2:
The patent changes the parameter of clock division ratio to resolve the contradiction. By adjusting the division ratio of the clock signal fed to the shift register, the system can achieve different effective latency counts using the same physical hardware. This parameter change allows one circuit to perform multiple functions that would otherwise require many separate flip-flops.
2Adaptability or versatility
If many flip-flops are implemented to count a wide range of latencies, then the latency counting capability is improved, but the consumption current increases
Solution Approach 1:
The patent implements universality by designing a single shift register that can function for multiple latency values through adjustable clock division. Instead of having dedicated flip-flops for each latency value, one universal shift register structure serves all latency counting needs by changing the clock division ratio, thereby reducing total component count and power consumption.
Solution Approach 2:
The dynamic adjustment of clock division ratio allows the system to optimize power consumption for different operating conditions. When a smaller latency is needed, a lower division ratio is used, activating fewer logic stages effectively, which reduces dynamic power consumption compared to always having maximum-latency hardware ready.
3Measurement precision
If the command signal is transmitted through many flip-flops during high-speed operation, then the latency counting accuracy is improved, but the charge/discharge currents increase
Solution Approach 1:
The patent changes the clock division ratio parameter to optimize the balance between counting accuracy and power consumption. By selecting appropriate division ratios based on the required latency, the system achieves accurate counting while minimizing the number of active flip-flop stages, thereby reducing charge/discharge currents during high-speed operation.
4Manufacturing precision
If latency counters are provided for respective latencies, then the latency control precision is improved, but the circuit scale remarkably increases
Solution Approach 1:
The patent creates a universal latency counter based on a single shift register that can be configured for different latency requirements through clock division ratio adjustment. This multi-functional approach eliminates the need for separate dedicated counters for each latency type, achieving precise latency control while keeping the circuit scale manageable.
Data Source
AI summary
A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.