3D Semiconductor Package Cover for Heat and Transmission Loss

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Solution Overview

Problem

The integration of multiple semiconductor devices in miniaturized electronic apparatus poses challenges due to the need for advanced packaging and assembling techniques that enhance electrical performance and reduce transmission and insertion losses.

Innovation Solution

A semiconductor device manufacturing method involving a circuit substrate with build-up layers, semiconductor packages connected via interposers and underfills, and a metallic cover with grooves to improve thermal dissipation and mechanical stability, allowing for efficient integration and testing of 3D packaging structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor devices are integrated in miniaturized electronic apparatus, then device functionality and performance are improved, but transmission loss and insertion loss increase

Engineering Contradiction:

Improvedevice integration capabilityVSAvoidtransmission loss

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent transitions from traditional 2D planar packaging to 3D vertical stacking architecture. Multiple semiconductor devices are stacked vertically on top of each other, utilizing the third dimension (height) to achieve higher integration density without increasing footprint area, thereby reducing transmission loss and insertion loss while maintaining device functionality

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested packaging where smaller semiconductor devices are embedded within or between larger structural layers. The devices are nested within a multi-layer substrate structure with intermediate transfer layers, allowing compact integration while maintaining electrical performance

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If advanced packaging techniques are used to integrate multiple semiconductor devices, then electrical performance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveelectrical performanceVSAvoidpackaging complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the packaging structure into distinct segments: substrate layers, intermediate transfer layers, and device layers. Each segment performs a specific function and can be processed independently, then assembled together. This segmentation simplifies the manufacturing process compared to monolithic advanced packaging while maintaining electrical performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate transfer layers as mediators between the substrate and semiconductor devices. These intermediate layers facilitate the bonding and alignment processes, simplifying the integration of multiple devices while maintaining electrical performance through controlled impedance pathways

Inventive Principle:

Principle #24Intermediary (Mediator)

3Volume of moving object

If semiconductor devices are miniaturized to reduce size, then device dimensions are reduced, but thermal dissipation becomes more difficult

Engineering Contradiction:

Improvedevice sizeVSAvoidthermal dissipation

Core Design Contradiction:

Volume of moving objectVSTemperature

Solution Approach 1:

The patent implements localized thermal management by incorporating thermal vias and heat dissipation structures at specific high-heat-generation locations within the stacked device architecture. Different regions of the package have different thermal properties optimized for their specific functions, allowing effective heat dissipation from miniaturized devices

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent uses multiple identical thermal via structures distributed throughout the package, copying the same thermal management geometry at different locations. This standardized approach to thermal dissipation efficiently manages heat from miniaturized devices while maintaining compact dimensions

Inventive Principle:

Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables improved electrical performance, reduced deformation under thermal stress, and enhanced reliability by facilitating effective heat dissipation and mechanical stability in semiconductor devices.

Implementation Method 1

reduced deformation under thermal stress

Methodology Applied

Scientific EffectThermal stress: Thermal Expansion

Implementation Method 2

improve thermal dissipation

Methodology Applied

Scientific EffectThermal dissipation: Conduction (thermal)

Data Source

PatentUS12170237B2Semiconductor structure and manufacturing method thereof

Publication Date: 2024.12.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.