Semiconductor Crack-Arrest Structure for Dielectric Dicing Damage

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Solution Overview

Problem

Mechanical wafer dicing processes in semiconductor manufacturing generate cracks in dielectric layers that propagate into the central region of semiconductor dies, affecting performance and reliability.

Innovation Solution

A semiconductor device with a crack arresting structure featuring a groove in the peripheral region, filled with a dielectric layer structure and a crack arresting structure that intersects tilted surfaces, preventing cracks from propagating into the central region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If mechanical wafer dicing processes are used to cut semiconductor wafers, then wafer dicing efficiency is improved, but cracks propagate from dicing streets into the central region of semiconductor dies

Engineering Contradiction:
Improvewafer dicing efficiencyVSAvoidcrack propagation resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The dielectric layer is segmented by forming a groove that extends through it, dividing the continuous dielectric layer into separate regions. This segmentation creates a physical barrier that stops crack propagation from the dicing street into the central region of the semiconductor die, while allowing the mechanical dicing process to continue efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A crack arresting structure is introduced as an intermediary element between the dicing street and the central region of the semiconductor die. This structure, formed in the groove and filled with conductive material, acts as a mediator that absorbs and stops crack energy, preventing cracks from reaching the functional central region while maintaining the efficiency of mechanical dicing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If crack stop structures are formed along the die edge to stop crack propagation, then crack propagation is arrested, but electric flashover risk increases between conductive structures

Engineering Contradiction:
Improvecrack propagation resistanceVSAvoidelectric flashover risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A dielectric layer is introduced as an intermediary insulating barrier between the crack arresting structure (formed with conductive material) and other conductive structures on the semiconductor die. This dielectric intermediary prevents direct electrical contact between the crack arresting structure and other conductive elements, eliminating the flashover risk while maintaining effective crack propagation arrest.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If dielectric layers laterally extend into dicing streets, then mechanical stress is distributed, but cracks still propagate into the central region of semiconductor dies

Engineering Contradiction:
Improvemechanical stress distributionVSAvoidcrack propagation resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The continuous dielectric layer that laterally extends into the dicing street is segmented by forming a groove through it. This segmentation creates a discontinuity that acts as a crack arrester, allowing the dielectric to provide mechanical stress distribution in functional regions while preventing crack propagation from the dicing street into the central region of the semiconductor die.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250273600A1Semiconductor device having a crack arresting structure and method of manufacturing
Publication Date: 2025.08.28 INFINEON TECH AUSTRIA AG
  • US20250273600A1 patent drawing
  • US20250273600A1 patent drawing
  • US20250273600A1 patent drawing

AI summary

A semiconductor device includes a semiconductor portion including a central region and a peripheral region separating the central region from a lateral chip edge. An interlayer dielectric is formed on a horizontal first main surface of the semiconductor portion. In the peripheral region, a groove extends through the interlayer dielectric. A crack arresting structure includes a first portion formed in the groove. A dielectric layer structure is formed on the interlayer dielectric and the crack arresting structure. The dielectric layer structure and the crack arresting structure are configured such that each horizontal plane intersecting the dielectric layer structure and the lateral chip edge intersects a tilted surface of the dielectric layer structure in the peripheral region.