Crack Arrest Structures in Semiconductor Die
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Solution Overview
Problem
Semiconductor devices experience stress-induced delamination due to material property differences, particularly when low dielectric constant materials are used for interlayer dielectric layers, leading to cracks and electrical failures.
Innovation Solution
The implementation of a crack arrest structure with curva-linear or polygon-shaped metal features, including vias, formed in a stair-step pattern across all metal layers in high-stress areas to divert crack propagation away from active circuit regions, reducing stress concentration and impeding delamination in the x-y plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low dielectric constant materials are used for interlayer dielectric layers to improve device performance, then device performance is improved, but delamination propensity increases
Solution Approach 1:
The patent divides the continuous interlayer dielectric structure into segmented regions by introducing crack arrest features (metal structures arranged in specific patterns) that create discontinuities in the stress propagation path. These features segment the low dielectric constant material layers, preventing continuous delamination while preserving the performance benefits of the low-k material in active regions.
Solution Approach 2:
The patent introduces metal structures (via holes, trenches, or patterned layers) as intermediary elements between the low dielectric constant material layers and the substrate. These intermediary features act as stress barriers that mediate the stress transfer, preventing direct stress propagation through the vulnerable low-k material interfaces and thereby reducing delamination.
2Stress or pressure
If stress relief cracks are allowed to propagate to relieve material stress, then stress is reduced, but electrical failures and loss of functionality occur
Solution Approach 1:
The patent extracts or removes the harmful stress concentration from the active circuit regions by positioning crack arrest features specifically in high-stress areas such as die edges and corners. The metal structures are strategically placed to intercept and redirect stress-induced cracks before they can propagate into functional regions, effectively taking out the stress relief mechanism from the problematic areas while preserving device functionality.
Solution Approach 2:
The patent applies preliminary anti-action by pre-positioning crack arrest features (metal structures in predetermined patterns) in high-stress regions before stress-induced cracks can form and propagate. These pre-placed features create barriers that prevent crack initiation and propagation in advance, countering the harmful stress effects before they can damage the device functionality.
Data Source
AI summary
A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.