Semiconductor Module Crosslink Wiring for Flexible Signal Routing
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Solution Overview
Problem
Existing semiconductor systems require different wiring designs for each application, necessitating the production of multiple devices with specific specifications, which increases complexity and can lead to electrical characteristic deterioration due to extended wiring lengths.
Innovation Solution
A semiconductor device with a crosslinking wiring configuration that allows flexible signal line connections between stacked semiconductor modules, enabling adaptation to various specifications without altering the mounting substrate's wiring layout, thereby allowing a single device to be diverted to different specifications as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different wiring designs are created for each application, then the semiconductor device can be adapted to specific specifications, but the device complexity and production variety increase
Solution Approach 1:
The patent implements a universal wiring substrate design where signal lines are routed to extend beyond the mounting substrate boundaries. This allows a single wiring design to serve multiple applications by simply changing how the semiconductor chips are connected to the extended signal lines, rather than creating different wiring designs for each application.
Solution Approach 2:
The patent separates the wiring design into two independent parts: the mounting substrate wiring (which remains fixed and universal) and the chip connection configuration (which can be varied). This segmentation allows the wiring substrate to be reused across different applications while adapting the chip connections to meet specific specification requirements.
2Adaptability or versatility
If wiring length is extended to accommodate different specifications, then adaptability increases, but electrical characteristic deterioration occurs
Solution Approach 1:
The patent pre-routes signal lines on the wiring substrate to extend beyond the mounting substrate boundaries before chip mounting. This preliminary action ensures that signal lines of appropriate lengths are already in place, allowing chips to be connected to these pre-prepared lines without requiring extended wiring that would deteriorate electrical characteristics.
Solution Approach 2:
The patent utilizes the spatial dimension by extending signal lines in the planar direction on the wiring substrate rather than increasing wiring length in the vertical or lateral expansion direction. This allows adaptation to different specifications by reconfiguring chip connections to existing extended signal lines without extending the actual wiring length.
3Adaptability or versatility
If multiple device specifications are produced, then application coverage increases, but manufacturing efficiency decreases
Solution Approach 1:
The patent creates a universal wiring substrate that can serve multiple applications, eliminating the need to produce different wiring designs for different specifications. A single wiring substrate design can be used across all applications by varying only the chip connection configuration, thereby maintaining high manufacturing efficiency while achieving broad application coverage.
Solution Approach 2:
The patent introduces flexibility at the chip connection level rather than at the wiring substrate level. This dynamic approach allows the same wiring substrate to be adapted to different specifications by changing how chips are connected to the extended signal lines, enabling application coverage without sacrificing manufacturing efficiency.
Data Source
AI summary
A semiconductor device includes a first semiconductor module and a second semiconductor module; a wiring substrate including the first and the second semiconductor modules mounted on a first surface, a first signal line connecting a first electrode provided on a second surface to the first semiconductor module, a second signal line connecting a second electrode provided on the second surface to the second semiconductor module, a third signal line connected to the first signal line, and a fourth signal line connected to the second signal line; and a crosslinking wiring that connects end portions of the third and the fourth signal lines to each other. A first signal is input to and output from at least one of the first semiconductor module or the second semiconductor module through the first and second signal lines.