Semiconductor Structure With CTE Gradient Insulation
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Solution Overview
Problem
The increasing complexity in manufacturing semiconductor structures with high interconnect density leads to issues such as degraded electrical performance and high yield loss, particularly when embedding electronic devices in coreless substrates, which can result in warpage and poor connections.
Innovation Solution
A semiconductor structure is designed with a layered insulation configuration, where the second insulation has a higher coefficient of thermal expansion (CTE) than the first and third insulations, ensuring matched shear strength and low warpage, and embedding an electronic device within the coreless layer with a CTE gradient distribution to minimize strain and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If electronic devices are embedded in coreless substrates to increase interconnect density, then device functionality and integration are improved, but substrate warpage and connection quality deteriorate
Solution Approach 1:
The patent changes the physical parameters of the insulation layers by introducing a CTE gradient distribution through multiple insulation layers with different coefficients of thermal expansion. This parameter modification allows the structure to accommodate thermal stress differently, preventing warpage while maintaining high interconnect density and reliable connections.
Solution Approach 2:
The patent uses composite insulation layer structures with different material properties (different CTE values) to create a gradient distribution. This composite approach allows the substrate to handle thermal expansion stresses more effectively, preventing warpage and improving connection reliability while maintaining high device density.
2Adaptability or versatility
If manufacturing operations are increased to achieve higher functionality and compact scale, then device performance is improved, but manufacturing complexity and yield loss increase
Solution Approach 1:
By modifying the structural parameters of the insulation layers (CTE gradient), the patent reduces manufacturing complexity. The gradient structure naturally accommodates thermal stress, eliminating the need for complex warpage compensation processes and reducing yield loss while maintaining high device functionality.
3Stability of the object's composition
If insulation layers with different CTE are used to reduce warpage, then structural stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating a CTE gradient where different insulation layers have different thermal expansion properties tailored to specific regions of the substrate. This localized approach to thermal management improves structural stability while the gradient distribution naturally compensates for variations, reducing the need for extremely precise CTE matching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances bandwidth, reliability, and reduces warpage, maintaining high electronic device density while preventing substrate warpage and improving manufacturing yield.
Implementation Method 1
a second insulation 120 over the first insulation 110, a third insulation 130 over the second insulation 120, a first conductor 210 proximal to a boundary 115 between the first insulation 110 and the second insulation 120, and an electronic device 300 electrically connected to the first conductor 210 and at least partially surrounded by the second insulation 120. A coefficient of thermal expansion (CTE) of the second insulation 120 is larger than a CTE of the first insulation 110 and a CTE of the third insulation 130
Data Source
AI summary
The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.