Semiconductor Current Suppression Layers for HVIC Noise Immunity
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Solution Overview
Problem
High-voltage integrated circuits (HVICs) face challenges in suppressing parasitic elements, particularly in the high-side circuit area, which can lead to noise immunity issues and operational failures due to large current flow and heat generation, complicating the manufacturing process.
Innovation Solution
The implementation of a semiconductor integrated circuit structure with a first well region of one conductivity type, a second well region of another conductivity type, and current suppression layers with higher impurity concentrations, strategically positioned to suppress parasitic element operations and enhance noise immunity without requiring complex manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current suppression layers with higher impurity concentrations are introduced to suppress parasitic element operations, then noise immunity and reliability are improved, but device structure and manufacturing process become more complex
Solution Approach 1:
The current suppression function is divided into multiple discrete layers: a first current suppression layer of the second conductivity type and a second current suppression layer of the first conductivity type. These layers are positioned at different depths below the first well region, creating segmented suppression zones that collectively reduce parasitic element operations while maintaining a manageable structural complexity
Solution Approach 2:
The current suppression layers are strategically positioned only in the lower portion of the base-body directly below the first well region, rather than throughout the entire device. This localized approach concentrates the suppression function where parasitic elements are most problematic (immediately below the high-side circuit arrangement area) while avoiding unnecessary complexity in other regions
2Reliability
If current suppression layers are positioned directly under the first well region, then parasitic element operation is suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The first and second current suppression layers are formed during the preliminary stages of device fabrication, before the active circuit elements are constructed above them. By establishing the suppression layers early in the manufacturing process on the base-body, the structure is pre-configured to suppress parasitic elements, and subsequent manufacturing steps can proceed with standard precision requirements rather than requiring high-precision alignment of suppression features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the operation of parasitic p-n-p bipolar transistors, improving noise immunity and reliability by forming potential barriers and reducing current amplification, thus preventing malfunction and heat-related issues.
Implementation Method 1
having an impurity concentration higher than that of the base-body... forming potential barriers and reducing current amplification
Data Source
AI summary
A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.