Semiconductor Device Current-Carrying Test Method
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges such as high costs, reduced productivity, and increased temperature issues during current-carrying tests due to the need for individual chip testing, which can lead to defects and inefficiencies in the production of semiconductor devices with P-N junction diodes.
Innovation Solution
A method where the back surface of multiple current-carrying semiconductor elements with P-N junction diodes is connected to a conductor plate, and a conductor piece is connected to the front surface, allowing for simultaneous testing of P-N junction diodes in an intermediate product of a semiconductor device, thereby reducing temperature increase and testing time, and utilizing the conductor piece for electrode bonding, eliminating the need for protective metal foil.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current-carrying test is conducted chip by chip with individual testing, then testing precision is improved, but productivity deteriorates
Solution Approach 1:
The patent combines multiple semiconductor chips into a single test unit by mounting them on a common substrate with shared electrode structures. This allows simultaneous current-carrying testing of multiple chips through a single test connection, maintaining testing precision while dramatically improving productivity by reducing the number of individual test operations required.
Solution Approach 2:
The substrate structure serves multiple functions: it acts as both the mounting platform for multiple chips and as part of the test electrode system. The common electrode structure on the substrate enables universal testing across multiple chips simultaneously, eliminating the need for separate test apparatus for each chip.
2Loss of time
If test temperature is increased to reduce current application time, then testing speed is improved, but electrode degradation worsens
Solution Approach 1:
The patent changes the test configuration from individual chip testing to multi-chip simultaneous testing on a common substrate. This structural parameter change allows for optimized current density distribution and heat dissipation, enabling effective testing at moderate temperatures without excessive electrode degradation, thus balancing testing speed with electrode reliability.
3Loss of time
If current density is increased to reduce testing time, then testing efficiency is improved, but test condition strictness worsens
Solution Approach 1:
By combining multiple chips on a common substrate with shared electrodes, the patent enables distributed current paths that reduce the strictness of test conditions for each individual chip while maintaining overall testing efficiency. The multi-chip configuration allows for more flexible current density management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves semiconductor device productivity by enabling simultaneous testing of multiple semiconductor elements, reduces testing costs, and effectively manages heat generated during the current-carrying test, minimizing temperature increases and potential defects.
Implementation Method 1
heat generated by the semiconductor element during the current-carrying test may be trapped inside the semiconductor device, raising temperature inside the semiconductor device
Implementation Method 2
In a case where forward current is applied to a MOSFET using SiC, bipolar degradation may occur in which forward voltage increases with expanding lamination defects
Implementation Method 3
a buffer layer is formed on a substrate, and a drift layer is formed on the buffer layer, so that bipolar current does not reach a lamination defect in the substrate
Data Source
AI summary
In a method for manufacturing a semiconductor device, a back surface of each of plurality of current-carrying semiconductor elements each having a plurality of P-N junction diodes built-in is connected to a first principal surface of a conductor plate. Further, a conductor piece is connected to a front surface of each of the plurality of current-carrying semiconductor elements. Then, a current-carrying test is conducted on the plurality of P-N junction diodes with a second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece.