Semiconductor Cut Mask Method for 10 nm Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High precision in dimension and position is required for cut patterns in semiconductor manufacturing using 1D layouts, but existing methods struggle to achieve sufficient dimensional and positional precision, especially at the 10 nm or less node scale.
Innovation Solution
A semiconductor device manufacturing method involving a first pattern forming step with a first cut mask and a second pattern forming step using a second cut mask, where both masks consist of openings or light shielding portions of equal shapes, with shrinking or slimming processes applied to the resist patterns to enhance precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional cut pattern method is used to form fine mask patterns, then the pattern can be formed using standard photolithography, but the positional precision and dimensional accuracy deteriorate at 10 nm or less node scale
Solution Approach 1:
The patent divides the pattern formation process into multiple discrete steps: forming a first pattern with lines and spaces, creating a first cut mask, forming a second pattern, and creating a second cut mask. Each step uses equal-shaped openings or light shielding portions, segmenting the complex high-precision patterning into manageable stages that collectively achieve the required 10 nm or less precision without exceeding photolithography resolution limits.
2Length of moving object
If the cut pattern dimensions are reduced to achieve finer features, then the pattern resolution improves, but the positional precision and shape consistency deteriorate
Solution Approach 1:
The patent applies local quality by ensuring that each cut mask contains openings or light shielding portions of equal shapes at different positions. This local uniformity in shape and size, combined with the specific arrangement in the first and second cut masks, maintains shape consistency and positional precision even as the overall pattern dimensions are reduced to achieve finer features at 10 nm or less node scale.
Data Source
AI summary
Disclosed is a method for manufacturing a semiconductor device. The method includes: a first pattern forming step of forming, on a pattern forming target film, a first film that is patterned to have a first pattern that includes lines which are aligned with each other with spaces of a predetermined interval being interposed therebetween, and include a portion separated by using a first cut mask; a step of forming a second film to cover a surface of the first film; and a second pattern forming step of forming a pattern forming target film that is patterned to have a second pattern, by separating a portion of the space of the first step using a second cut mask. The first and second cut mask includes a plurality of openings or light shielding portions that have equal shapes, respectively.