Semiconductor Daisy Chain RDL Bonding Reliability Evaluation
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased manufacturing complexity, resulting in issues such as poor electrical interconnection and delamination, which cause high yield loss due to the complexity of modifying and improving semiconductor device structures and manufacturing operations.
Innovation Solution
A semiconductor structure and method involving a first die, a redistribution layer, and a second die electrically connected through the redistribution layer, with a daisy chain embedded for evaluating the reliability of bonding between the second die and the redistribution layer by measuring electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the manufacturing complexity increases and leads to poor electrical interconnection and delamination
Solution Approach 1:
The patent divides the semiconductor device into multiple separate layers including a substrate layer, a first interlayer dielectric layer, a conductive layer, a second interlayer dielectric layer, and a cap layer. Each layer can be independently manufactured and tested, reducing the complexity of manufacturing the entire device at once while maintaining high integration density.
Solution Approach 2:
The patent performs electrical resistance measurements on the conductive layer before completing the full device assembly. This preliminary testing allows for early detection of manufacturing defects such as poor electrical interconnection, enabling corrective actions before further processing steps are performed, thereby reducing yield loss.
2Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but delamination and yield loss increase
Solution Approach 1:
The patent performs electrical resistance measurements on the conductive layer before completing the full device assembly. This preliminary testing allows for early detection of manufacturing defects such as poor electrical interconnection, enabling corrective actions before further processing steps are performed, thereby reducing yield loss.
Solution Approach 2:
The patent implements a feedback mechanism where electrical resistance measurements are used to evaluate the quality of the conductive layer and bonding interfaces. Based on these measurements, manufacturing parameters can be adjusted to improve bonding reliability and prevent delamination in subsequent production batches.
3Quantity of substance
If manufacturing operations are performed on miniaturized semiconductor devices, then higher integration density is achieved, but the complexity of manufacturing increases and causes poor electrical interconnection
Solution Approach 1:
The patent performs electrical resistance measurements on the conductive layer before completing the full device assembly. This preliminary testing allows for early detection of manufacturing defects such as poor electrical interconnection, enabling corrective actions before further processing steps are performed, thereby reducing yield loss.
Solution Approach 2:
The patent replaces complex mechanical assembly and testing operations with electrical resistance measurements to evaluate bonding quality. This substitution of measurement methodology provides a non-destructive, precise way to assess interconnection quality without requiring physical disassembly or complex mechanical testing equipment.
4Ease of manufacture
If the structure of semiconductor devices is modified to improve manufacturing, then manufacturing operations become easier, but the complexity of modifying the structure increases
Solution Approach 1:
The patent divides the semiconductor device into multiple separate layers including a substrate layer, a first interlayer dielectric layer, a conductive layer, a second interlayer dielectric layer, and a cap layer. Each layer can be independently manufactured and tested, reducing the complexity of manufacturing the entire device at once while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively evaluates and ensures the reliability of bonding between the second die and the redistribution layer, reducing yield loss and improving manufacturing efficiency by detecting potential failures through electrical resistance measurements.
Implementation Method 1
evaluating a reliability of a bonding between the second die and the redistribution layer by measuring electrical resistance
Data Source
AI summary
A semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.