Semiconductor Package Dam and Trench Underfill Voids
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Solution Overview
Problem
In conventional semiconductor packages, especially large-size 2.5D packages, it takes a long time to fill the space between the semiconductor chip and the package substrate with underfill material, leading to a high risk of voids, such as bubbles, being trapped, which can cause short circuits due to moisture absorption.
Innovation Solution
Incorporating a dam and a trench on the package substrate to divide the underfill into discontinuous sections, allowing for faster filling and preventing voids from forming by creating an air passage for air discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the space between the semiconductor chip and package substrate is filled with underfill material from an edge portion in a conventional large-size package, then the filling process can be completed, but it takes a long time to fill the space and there is a high risk of voids such as bubbles being trapped in the filling material
Solution Approach 1:
The patent divides the underfill filling process into multiple independent sections by introducing dams and trenches. The underfill is filled in separate regions simultaneously rather than as one continuous flow, which reduces the overall filling time and prevents air entrapment by creating controlled filling zones with defined air escape paths.
Solution Approach 2:
The patent introduces a vertical dimension by creating trenches (downward cavities) and dams (protruding structures) in the package substrate. This three-dimensional structure transforms the traditional two-dimensional planar filling process, creating air passages that allow trapped air to escape vertically while the underfill flows horizontally, thereby preventing void formation.
2Productivity
If the underfill is filled quickly to reduce filling time, then productivity is improved, but the risk of voids and bubbles being trapped increases
Solution Approach 1:
By segmenting the filling space into multiple independent regions using dams and trenches, each region can be filled rapidly without causing air entrapment. The segmentation creates controlled flow paths that maintain high filling speed while preventing void formation through proper air discharge channels in each segment.
Solution Approach 2:
The dams and trenches act as intermediary structures that mediate between the fast-flowing underfill and the trapped air. These structures create controlled air passages that allow air to escape gradually while the underfill flows quickly, preventing void formation even at high filling speeds.
3Loss of time
If dams and trenches are introduced to divide the underfill into sections, then the filling time is reduced and void prevention is improved, but the device complexity increases
Solution Approach 1:
The dams and trenches are merged with the package substrate as an integrated structure rather than being separate components. This combining approach reduces assembly steps and overall device complexity while still providing the functional benefits of segmented underfill filling and air passage creation.
Solution Approach 2:
The dams and trenches serve multiple functions simultaneously: they segment the underfill filling zones, create air discharge passages, and are integrated into the package substrate structure. This multi-functionality reduces the need for additional separate components, thereby minimizing the increase in device complexity while achieving the desired filling time reduction and void prevention.
Data Source
AI summary
A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, and a plurality of underfills between the package substrate and the semiconductor chip. The package substrate includes a trench formed in the package substrate and a plurality of dams on both sides of the trench, respectively. The top surfaces of the plurality of dams may be positioned at a lower level than the bottom surface of the semiconductor chip in a cross-sectional view of the semiconductor package with the package substrate providing a base reference level.