Semiconductor Dual Damascene Moisture Removal

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor manufacturing, moisture trapped in openings during the dual damascene process leads to defects like voids in copper material, increasing contact resistance and impacting device performance, especially as critical dimensions are miniaturized.

Innovation Solution

A semiconductor process involving a cleaning step with a dilute solution of HF and H2SO4 followed by a baking step at 200° C. to 300° C. for 30 minutes to 60 minutes is conducted between the formation of the barrier layer and the filling of the conductive layer, effectively removing moisture and impurities from the opening.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the opening is filled with copper material after barrier layer formation without intermediate treatment, then the manufacturing process is simple and fast, but moisture trapped in the opening causes voids in copper material and increases contact resistance

Engineering Contradiction:
Improvedevice performanceVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing a cleaning step with dilute HF and H2SO4 solution followed by a baking step at 200-300°C for 30-60 minutes between barrier layer formation and copper filling. This preliminary treatment removes moisture and organic contaminants from the opening surface before copper deposition, preventing void formation and ensuring reliable electrical contact, thus resolving the contradiction between process simplicity and device reliability.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the critical dimensions of the opening are miniaturized to advance operating speed and performance, then the device performance is improved, but moisture removal becomes more difficult and defects increase

Engineering Contradiction:
Improveoperating speedVSAvoidopening dimension control
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by optimizing the cleaning solution composition (dilute HF 0.01-0.1 wt% and H2SO4 1-10 wt%) and baking parameters (temperature 200-300°C, time 30-60 minutes) to effectively remove moisture from miniaturized openings. This controlled parameter adjustment enables thorough moisture removal from sub-70 nm openings without damaging the barrier layer, thus resolving the contradiction between miniaturization for performance and manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If an idle time is maintained between barrier layer formation and copper filling, then the process is easy to control, but moisture accumulates in the opening causing voids and defects

Engineering Contradiction:
Improveprocess controlVSAvoidmaterial filling quality
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies the extraction principle by removing moisture and organic contaminants from the opening through a dedicated cleaning step using dilute HF and H2SO4 solution followed by baking. This extraction of harmful moisture during the idle period prevents subsequent void formation in copper filling, thus resolving the contradiction between ease of process control and material filling quality.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process prevents voids in the conductive layer, lowers contact resistance, and enhances device performance by ensuring thorough moisture removal, even at miniaturized dimensions.

Implementation Method 1

A first cleaning step is conducted using a first cleaning solution. The first cleaning solution contains HF and H2SO4

Methodology Applied
Scientific EffectChemical cleaning:

Implementation Method 2

A baking step is conducted after the first cleaning step. A temperature for conducting the baking step ranges between 200° C. and 300° C.

Methodology Applied
Scientific EffectEvaporation: Evaporation

Implementation Method 3

A first conductive layer is conformally formed on the surface of the opening

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS8252679B2Semiconductor process
Publication Date: 2012.08.28 UNITED MICROELECTRONICS CORP
  • US8252679B2 patent drawing
  • US8252679B2 patent drawing
  • US8252679B2 patent drawing

AI summary

A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer.