Semiconductor Data Bus Pitch Conversion Layout

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Solution Overview

Problem

In semiconductor memory devices, the regular arrangement of data buses and buffer circuits leads to a shortage of area allocation for circuit blocks like the internal voltage generating circuit, resulting in increased chip area due to inefficient layout and unused free space.

Innovation Solution

The semiconductor device features data buses with different pitches over the memory cell and buffer areas, allowing for pitch conversion to match the widths of buffer and circuit block areas, optimizing the layout and reducing chip area by eliminating unnecessary free space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the arrangement pitch of buffer circuits is matched with the arrangement pitch of data buses, then the layout of buffer circuits becomes simplest, but the layout of other circuit blocks such as internal voltage generating circuit is considerably limited

Engineering Contradiction:
Improvelayout simplicityVSAvoidlayout flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The peripheral circuit area is divided into a buffer area and a circuit block area, with data buses extending through both areas. This segmentation allows different pitch arrangements in different regions, enabling simple buffer circuit layout while providing flexibility for other circuit blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different arrangement pitches are applied to different regions: the buffer area uses a first pitch matching the data bus pitch for simplicity, while the circuit block area uses a second pitch for flexibility. This local differentiation resolves the contradiction between layout simplicity and adaptability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8848460B2Semiconductor device having plural data buses and plural buffer circuits connected to data buses
Publication Date: 2014.09.30 LONGITUDE LICENSING LTD
  • US8848460B2 patent drawing
  • US8848460B2 patent drawing
  • US8848460B2 patent drawing

AI summary

A plurality of buffer circuits and data buses coupled to the buffer circuits are included in a device. Each of the data buses includes first and second portions. The first portions of the data buses are arranged at a first pitch in the second direction, and the second portions of the data buses are arranged at a second pitch in the second direction, the second pitch being smaller than the first pitch.