Semiconductor Device Bank Interleaving Data Bus Switching
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in data transfer due to the need for waiting times between read and write commands, particularly in stacked memory configurations where data buses are shared, leading to reduced data transfer efficiency and increased wiring density challenges.
Innovation Solution
A semiconductor device design that includes separate data buses for read and write operations, with a logic chip that switches between these buses based on command types, preventing collisions and allowing simultaneous issuance of read and write commands without waiting times, thereby optimizing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate data buses for read and write operations are provided, then data transfer efficiency is improved and waiting times are eliminated, but the number of wires doubles and wiring density increases
Solution Approach 1:
The patent implements dynamic switching of the data bus function between read and write operations using a switch element. The same physical data bus is dynamically allocated to different operations based on the current command being executed, eliminating the need for separate dedicated buses while preventing read-write collisions through temporal separation controlled by the switch.
Solution Approach 2:
The data bus is designed to serve multiple functions - it acts as a read data bus during read operations and as a write data bus during write operations. This multi-functional design allows a single bus structure to replace what would traditionally require two separate buses, reducing wiring complexity while maintaining the ability to prevent read-write collisions through functional separation in time.
2Speed
If via wires are used for inter-chip wiring in stacked memory, then data transfer between chips is enabled, but the wire diameter is 20 μm which is larger than in-plane wire by a digit or more, making it impossible to form a large number of via wires in limited area
Solution Approach 1:
The patent merges the read data bus and write data bus into a single shared data bus structure for inter-chip communication. By combining these functions into one bus that is dynamically switched between read and write modes, the number of via wires required is halved, allowing the same chip area to accommodate the necessary wiring while maintaining high-speed data transfer capabilities.
Data Source
AI summary
A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.