Semiconductor Data Control Unit Serial Parallel Conversion Test Mode
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Solution Overview
Problem
Existing semiconductor devices require processing to convert serial data to parallel data in normal operation mode, which is inefficient and can cause damage during testing due to increased probe card movement and potential interference between write units.
Innovation Solution
A semiconductor device with a data control unit that outputs parallel data in normal operation mode and converts serial data to parallel data in test mode, using a serial/parallel converter circuit and switch unit to provide arbitrary data patterns to write units, reducing probe card movement and enabling interference testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial data is applied in normal operation mode and converted to parallel data, then data can be written to multiple memory cells, but processing overhead increases and efficiency decreases
Solution Approach 1:
The patent applies dynamics by making the data input mode configurable - the semiconductor device can dynamically switch between accepting parallel data directly in normal operation mode and accepting serial data in test mode. This is achieved through mode control logic that reconfigures the data path based on operational requirements, eliminating unnecessary conversion processing in normal operation while maintaining test capability.
Solution Approach 2:
The patent changes the parameter of data input format from fixed to variable. By introducing a mode control signal that can set the device to either normal operation mode (parallel data input) or test mode (serial data input), the system adapts its data processing behavior based on the operational parameter, thereby optimizing efficiency for normal operations while preserving test functionality.
2Reliability
If probe card movement is increased to connect to multiple terminals for testing, then all terminals can be tested, but damage risk increases
Solution Approach 1:
The patent applies universality by designing the test interface to handle multiple testing functions through a single terminal. The serial data input terminal can serve both normal operation data input and comprehensive test data input, eliminating the need for separate test terminals. This multi-functional design reduces probe card movement while maintaining complete testing capability across all memory cells.
Solution Approach 2:
The patent merges the test data input function with the normal operation data input function by using the same terminal (DQ0) for both purposes. By combining these functions, the system eliminates the need for additional probe connections, thereby reducing mechanical stress and damage risk while maintaining complete test coverage through serial-to-parallel conversion.
3Device complexity
If only same content data is provided to write units in test mode, then terminal reduction is achieved, but interference testing capability is lost
Solution Approach 1:
The patent applies preliminary action by pre-configuring the serial-to-parallel conversion mechanism to generate diverse data patterns before they are needed for testing. The conversion circuit is designed in advance to accept serial data and expand it into parallel data with controlled variations, enabling interference testing without requiring complex real-time data generation logic during test execution.
Data Source
AI summary
A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts serial data applied to a particular terminal, which is one of the plurality of terminals, to parallel data, and outputs the parallel data to which the serial data applied to the particular terminal is converted to the plurality of drive units in a test mode.