Semiconductor Data Driver With Segmented Output Stages
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Solution Overview
Problem
Existing semiconductor data drivers for liquid crystal display devices experience significant distortion and delay in output waveforms due to back-bias voltage effects on Nch output transistors, leading to inefficient driving of data lines during column-inversion driving methods.
Innovation Solution
A semiconductor device with a differential circuit configuration that includes multiple output stages connected in parallel, using high-level, mid-level, and low-level power supplies to minimize back-bias voltage effects, ensuring minimal distortion and delay by controlling the activation states of output stages to prevent capacitance coupling between gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single output stage is used to drive data lines directly, then the circuit complexity is reduced, but the driving capability and waveform quality deteriorate due to back-bias voltage effects
Solution Approach 1:
The output circuit is divided into multiple independent output stages (first output stage, second output stage, third output stage, fourth output stage) that can be selectively activated. Each stage has its own transistors and control mechanisms, allowing the circuit to segment the driving function across multiple parallel paths to eliminate back-bias voltage effects and improve waveform quality.
2Power
If multiple output stages are used in parallel, then the driving capability is improved, but the device complexity increases
Solution Approach 1:
The circuit employs dynamic switching control where the activation state of each output stage changes based on the data period phase. During first data period, first and third stages are active while second and fourth stages are inactive; during second data period, the activation states are reversed. This dynamic reconfiguration allows multiple stages to share the driving burden without requiring all stages to be permanently active, thus improving driving capability while managing complexity.
Solution Approach 2:
Each output stage is designed with identical transistor configurations and control mechanisms, making them universal functional units. The first and second output stages share the same structure, as do the third and fourth stages. This universality allows the circuit to achieve high driving capability through parallel operation while reducing design complexity by reusing the same circuit block multiple times.
3Speed
If output stages are continuously active, then the driving response is immediate, but capacitance coupling between gates causes distortion and delay
Solution Approach 1:
The circuit proactively prevents capacitance coupling distortion by ensuring that only one output stage is active at any given time through complementary activation control. The control circuit is designed so that when first and third stages are active, second and fourth stages are completely inactive, and vice versa. This preliminary anti-action eliminates the possibility of simultaneous conduction and associated capacitance coupling, maintaining waveform accuracy while preserving fast response through ready-to-switch design.
Data Source
AI summary
A semiconductor device for driving a load of an object includes a differential circuit receiving an input signal and outputting differential output signals, first to fourth output circuits receiving the differential output signals, and a control circuit configured to respectively connect or disconnect the differential circuit to each of the first to fourth output circuits. The first output circuit is connected between high-level and mid-level power supply terminals and outputs a first output signal to the differential circuit, the second output circuit is connected between the high-level and mid-level power supply terminals, and outputs a second output signal to the load, a third output circuit is connected between mid-level and low-level power supply terminals, and outputs a third output signal to the differential circuit, and a fourth output circuit is connected between the mid-level low-level power supply terminals, and outputs a fourth output signal to the load.