Semiconductor Data Output Circuit Dynamic I/O Switching

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Solution Overview

Problem

Semiconductor memory devices face data read failures due to coupling phenomena between segment I/O lines, exacerbated by rising power source voltages, which affect the amplification and output of fine signal levels.

Innovation Solution

A semiconductor device with a data output circuit that includes a bit line sense amplifier, a local sense amplifier, and a control signal generator to dynamically control the I/O switch control signal based on the power source voltage, coupling or separating segment and local I/O lines to mitigate coupling effects and ensure precise data amplification and output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the power source voltage is increased to improve the driving capability and signal strength, then the amplification capability is improved, but the coupling phenomenon between segment I/O lines is exacerbated causing data read failures

Engineering Contradiction:
Improvepower source voltageVSAvoiddata read reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies dynamics by making the switching unit's coupling state variable rather than fixed. The I/O switch control signal dynamically adjusts the coupling between segment I/O lines and local I/O lines based on operational requirements. During read operations, the switching unit separates these lines to prevent coupling phenomena, while during write operations, it couples them for proper data transmission, thus resolving the contradiction between power utilization and read reliability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by creating different electrical connection states for different operational modes. The switching unit selectively couples or separates specific line pairs (segment I/O lines with local I/O lines) depending on whether a read or write operation is being performed. This localized control of electrical connectivity ensures that during read operations, the segment I/O lines are isolated to prevent coupling-induced read failures, while during write operations, they are properly connected for data transmission

Inventive Principle:
Principle #3Local quality

2Productivity

If the segment I/O lines are coupled with local I/O lines to improve data transmission, then the writing operation is improved, but the coupling phenomenon causes data read failures

Engineering Contradiction:
Improvewriting operation efficiencyVSAvoiddata read reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamics through the switching unit that responds to operation mode signals. During write operations, the switching unit couples segment I/O lines with local I/O lines to enable efficient data transmission. During read operations, it separates these lines to prevent coupling phenomena. This dynamic reconfiguration allows the system to optimize for writing efficiency when needed while preventing read failures when performing read operations

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies periodic action through the periodic switching of coupling states based on alternating read and write operations. The switching unit periodically transitions between coupled and separated states in synchronization with the operational mode. This periodic reconfiguration ensures that coupling is present during write operations for efficient data transmission and absent during read operations to prevent read failures

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8908447B2Semiconductor device and data output circuit therefor
Publication Date: 2014.12.09 SK HYNIX INC
  • US8908447B2 patent drawing
  • US8908447B2 patent drawing
  • US8908447B2 patent drawing

AI summary

A semiconductor device includes a memory cell array configured to include a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, a bit line sense amplifier connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment I/O line, a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage, and a local sense amplifier connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line.