Semiconductor Bank Group Data Routing for MPR Area Reduction
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently managing multi-purpose registers (MPRs) in high-speed data transfer operations, particularly in next-generation memory products like DDR4 SDRAM, where the area occupied by MPRs and their I/O lines increases, affecting performance and efficiency.
Innovation Solution
A semiconductor device design that includes electrically isolated bank groups and a multi-purpose register capable of providing multi-purpose data in an MPR mode, with a route selection unit generating signals to route data between bank groups, enabling efficient external output of data through one MPR in a maximum data width option mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple MPRs are provided for each bank group to support maximum data width mode, then data output capability is improved, but area occupation and I/O line complexity increase
Solution Approach 1:
The patent makes the first data line GIO_BG0 serve multiple functions: it carries normal data from the first bank group BG0 during normal operations, and carries multi-purpose data from the second bank group BG1 during MPR operations. This is achieved through route control logic that dynamically switches the function of GIO_BG0 based on the operation mode, eliminating the need for dedicated I/O lines for MPR data and reducing overall I/O line complexity.
Solution Approach 2:
The patent merges the MPR data output path with the normal data path by routing multi-purpose data through the first data line GIO_BG0 that is already connected to external pins. The route providing logic combines the MPR data path and normal data path into a shared infrastructure, reducing the need for additional separate routing resources and minimizing area occupation.
2Reliability
If separate data lines are used for each bank group, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic routing where the function of data lines is not fixed but changes based on operation mode. The route selection unit dynamically switches between normal mode (separate data lines for each bank group) and MPR mode (shared data line for multi-purpose data). This dynamic approach maintains reliability through proper isolation during normal operations while reducing complexity through resource sharing during MPR operations.
Solution Approach 2:
The patent segments the operation into distinct modes (normal mode and MPR mode) with dedicated route control logic for each. The route providing logic is segmented into different functional paths that are activated based on the current operation mode, allowing separate data lines to be used when needed for reliability while enabling consolidation when appropriate to reduce complexity.
Data Source
AI summary
A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.