Semiconductor Device Data Storage Material Pattern Width Control
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Solution Overview
Problem
Next-generation semiconductor devices face challenges in achieving high integration density and low power consumption while maintaining reliable data storage and switching performance.
Innovation Solution
The semiconductor device design includes a specific structure with a switching material pattern, a data storage material pattern, and an upper conductive pattern, where the maximum width of the lower region of the data storage material pattern is less than the minimum width of the switching material pattern, and the maximum width of the upper conductive pattern is less than the upper region of the data storage material pattern, optimized with conductive lines and insulating patterns to prevent leaning defects and enhance durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the data storage material pattern and upper conductive pattern are designed with larger widths, then the manufacturing precision and reliability improve, but the integration density decreases
Solution Approach 1:
The patent transitions from a conventional planar structure to a three-dimensional stacked structure. The data storage material pattern and upper conductive pattern are arranged in vertical layers rather than horizontal planes, allowing multiple functional layers to occupy the same footprint area. This vertical stacking enables smaller pattern widths while maintaining adequate spacing between adjacent patterns, thereby improving integration density without sacrificing manufacturing precision
Solution Approach 2:
The patent implements a nested configuration where the upper conductive pattern is positioned within the horizontal projection area of the data storage material pattern, or vice versa. This nesting arrangement allows the patterns to share the same lateral space, effectively reducing the total device footprint while maintaining the required pattern dimensions for reliable manufacturing
2Productivity
If the pattern widths are reduced to increase integration density, then more devices fit on the substrate, but leaning defects occur reducing reliability
Solution Approach 1:
By stacking functional layers vertically, the patent reduces the lateral dimensions of individual patterns while maintaining structural integrity. The vertical arrangement provides natural mechanical support between layers, preventing the leaning defects that would occur in thinner lateral structures. This dimensional transition allows high integration density without compromising pattern stability
Solution Approach 2:
The patent incorporates intermediate layers and spacing structures between the data storage material pattern and upper conductive pattern that provide mechanical cushioning and support. These intermediate structures prevent direct contact and potential leaning between adjacent patterns, maintaining reliability even when pattern widths are reduced for higher integration density
Data Source
AI summary
A semiconductor device, includes: a first conductive structure on a substrate; a second conductive structure on the first conductive structure; and a first memory cell structure between the first conductive structure and the second conductive structure, wherein the first memory cell structure includes: a switching material pattern on the first conductive structure; a data storage material pattern on the switching material pattern; and an upper conductive pattern on the data storage material pattern, wherein a first width of a lower region of the data storage material pattern is less than a first width of the switching material pattern, and wherein a first width of the upper conductive pattern is less than a width of an upper region of the data storage material pattern.