Semiconductor Data Transfer Controller for Filter Arithmetic
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Solution Overview
Problem
Current microcomputer technologies face challenges in efficiently performing FIR and IIR filter arithmetic due to CPU processing delays during data transfer operations, which hinder the speed and accuracy of control operations, especially when handling multiple control targets with varying filter coefficients.
Innovation Solution
A semiconductor device with a data transfer controller that enables concurrent data transfer and arithmetic operations by utilizing a data transfer controller to efficiently supply data to a filter arithmetic unit, allowing for continuous data transfer and chain operations across multiple registers, thereby enhancing processing speed and reducing physical scale requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed by CPU during interrupt processing, then data transfer can be completed, but the operating time of CPU is prolonged and processing efficiency is reduced
Solution Approach 1:
The patent extracts the data transfer function from the CPU and implements it as a separate DMA (Direct Memory Access) controller. This allows data transfer operations to be performed independently by the DMA controller without occupying the CPU, thereby resolving the contradiction between completing data transfer and maintaining CPU processing efficiency.
Solution Approach 2:
The patent introduces a DMA controller as an intermediary between the memory and I/O devices. This intermediary handles all data transfer operations, including block transfer and repeat transfer modes, eliminating the need for CPU intervention in data transfer and thus preventing CPU time loss.
2Productivity
If hardware resources are increased to improve data transfer capability, then data transfer performance is improved, but device complexity and physical scale increase
Solution Approach 1:
The patent implements a universal DMA controller that can perform multiple data transfer functions including block transfer mode and repeat transfer mode through software configuration rather than dedicated hardware for each mode. This multi-functionality approach improves data transfer capability while avoiding the need for separate hardware circuits for each transfer type, thus controlling device complexity.
Solution Approach 2:
The patent uses dynamic configuration where the same DMA controller can switch between different transfer modes (block transfer, repeat transfer) based on software settings. This dynamic adaptability allows the system to optimize data transfer performance for different applications without requiring fixed, complex hardware for each specific function.
3Adaptability or versatility
If RAM is used for storing data transfer information, then data can be updated during transfer, but it is difficult to manage data transfer and update operations simultaneously
Solution Approach 1:
The patent segments the memory space into distinct areas: a vector table area for storing transfer control information and a data area for actual data transfer. This segmentation allows the DMA controller to independently manage vector table updates and data transfer operations without interference, resolving the contradiction between data update capability and management complexity.
Solution Approach 2:
The patent uses the vector table as an intermediary structure that mediates between the CPU and the DMA controller. The vector table stores transfer control information that the DMA controller reads and executes, allowing the CPU to update transfer parameters without directly interfering with ongoing data transfer operations, thus simplifying simultaneous management of data transfer and updates.
Data Source
AI summary
A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.