Semiconductor Data Transmission Device Test Mode Optimization
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Solution Overview
Problem
The programmable stress test for semiconductor memory apparatuses is inefficient due to the need for longer clock signal periods, which increases test time and production costs, especially as these devices become more integrated and operate at higher speeds, making it difficult to input commands quickly enough to perform normal data input/output operations effectively.
Innovation Solution
A data transmission device that operates in both normal and test modes, allowing for the direct application of test data to input/output lines without waiting for data from pads, reducing the time required for programmable stress tests by activating the enable signal every clock period in test mode, rather than every two or eight periods as in conventional schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the enable signal is activated every clock period in test mode, then the test time is significantly reduced, but the device must support dual operation modes (normal and test) increasing device complexity
Solution Approach 1:
The data transmission device dynamically switches between normal mode and test mode based on operational requirements. In normal mode, the enable signal is activated every other clock period for standard data input operations. In test mode, the enable signal is activated every clock period to accelerate testing. This dynamic mode switching allows the device to optimize performance for different operational contexts without permanent structural changes.
Solution Approach 2:
The device changes its operational parameters between normal and test modes. Specifically, the clock period utilization changes from every-other-clock activation in normal mode to every-clock activation in test mode. Additionally, the data input source parameter changes from external pad data in normal mode to internal test data in test mode. These parameter changes enable the device to achieve faster test times while maintaining normal operational integrity.
2Speed
If test data is directly applied to input/output lines without waiting for pad data, then the input time is reduced from 128 ns to 16 ns, but the device requires additional test data generation capability increasing device complexity
Solution Approach 1:
The device incorporates a test data generation block that pre-generates test data internally, eliminating the need to wait for external pad data during testing. This preliminary preparation of test data within the device allows immediate application to input/output lines, reducing input time from 128 ns to 16 ns. The test data generation capability is integrated into the device structure, enabling self-contained testing operations.
Solution Approach 2:
The test data generation block serves as an intermediary component that bridges the gap between the need for fast testing and the limitation of external data input. Instead of directly using external pad data which requires longer setup time, the intermediary test data generation block provides internally-generated test data that can be immediately applied to input/output lines, thus mediating the speed requirement while maintaining device functionality.
3Reliability
If the enable signal is activated every two or eight periods in normal mode, then data input operations are performed correctly, but the test time increases due to slower clock signal requirements
Solution Approach 1:
The device segments its operation into distinct normal mode and test mode pathways. In normal mode, the enable signal activation every other clock period ensures reliable data input operations with proper timing margins. In test mode, a separate pathway is activated where the enable signal can be applied every clock period with internally-generated test data. This segmentation allows each mode to be optimized independently - reliability for normal operation and speed for testing.
Solution Approach 2:
The data transmission device is designed with multi-functionality to handle both normal data input operations and accelerated test operations through a unified structure. The same data transmission device and input/output lines are used for both normal operation and testing, but with different operational parameters. This universal design allows the device to maintain reliability for correct data input while also achieving fast test times through mode switching, eliminating the need for separate testing hardware.
Data Source
AI summary
A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test data and output one of input data and test data as write data in response to an activation of a test enable signal, and a loading block configured to apply the write data to one of the plurality of global data input/output lines in response to an enable signal.