Semiconductor Debugging Break Detection and Subsystem Synchronization
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Solution Overview
Problem
Conventional debugging systems for multiprocessor semiconductor integrated circuit devices face challenges in accurately stopping only the target CPU core during debugging, as peripheral devices continue to operate, leading to incorrect internal state observations and inefficient data collection, and the low-speed external bus hampers trace data collection.
Innovation Solution
A semiconductor integrated circuit device with a break detecting unit and a stop control unit that synchronizes the stopping of subsystems based on debug-target information, allowing precise collection of debug-target information and improving debugging efficiency by using a high-speed internal bus for trace data storage and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a break condition is detected in a CPU core during debugging, then the CPU core execution is stopped, but peripheral devices continue to operate causing internal state changes
Solution Approach 1:
The system segments the stopping control by introducing a stop control unit that can independently control each subsystem (CPU core or peripheral device) based on debug-target information. This allows selective stopping of only the targeted subsystem while leaving others operational, preventing unwanted internal state changes in non-targeted components.
Solution Approach 2:
A stop control unit is introduced as an intermediary component between the break detecting unit and the subsystems. This mediator receives break detection signals and debug-target information, then intelligently determines which subsystems should be stopped, preventing direct and uncontrolled stopping that would affect all components.
2Ease of operation
If all CPU cores are stopped when a break occurs, then debugging can proceed, but it becomes impossible to stop only the target CPU core
Solution Approach 1:
The system divides the stopping control into independent controllable units for each CPU core and peripheral device. The stop control unit uses debug-target information to identify which specific subsystem should be stopped, enabling precise targeting rather than blanket stopping of all CPU cores.
Solution Approach 2:
The stopping behavior is made dynamic and adaptive based on debug-target information. Rather than a fixed rule to stop all CPU cores, the system dynamically determines which subsystems to stop based on the current debugging target, providing flexibility in debugging control.
3Device complexity
If a low-speed external bus is used for debugging, then interface simplicity is maintained, but trace data collection efficiency is reduced
Solution Approach 1:
The data collection function is segmented into two paths: a high-speed internal bus for collecting trace data from subsystems, and a low-speed external bus for interfacing with the debug PC. This segmentation allows the internal high-speed path to efficiently gather data while the external interface remains simple.
Solution Approach 2:
A trace collecting unit is introduced as an intermediary that collects trace data from multiple subsystems through the high-speed internal bus before transferring it to the debug PC via the low-speed external bus. This mediator buffers and aggregates data, improving collection efficiency without requiring a high-speed external interface.
Data Source
AI summary
To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.