Semiconductor Debug Control via Segmented Chip Access Keys

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Solution Overview

Problem

Semiconductor devices with instruction RAMs face challenges in preventing data leakage during debugging, as conventional methods compromise security and development efficiency, especially when multiple chips are packaged together, and lack effective control over debugger connections.

Innovation Solution

A semiconductor device configuration that includes a volatile memory for storing instructions, a processing unit, a nonvolatile memory for storing another instruction group, a control signal output unit to manage debugging permissions, and a debug control unit to control debugging functions based on these signals, ensuring secure data protection and efficient debugging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a chip containing an instruction RAM is used to allow free program alterations and high-speed operation, then program flexibility and operation speed are improved, but security against data leakage during debugging deteriorates

Engineering Contradiction:
Improveprogram flexibilityVSAvoiddata leakage risk
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The system is segmented into multiple chips packaged together, with one chip dedicated to storing access keys in nonvolatile memory while another chip contains the instruction RAM. This segmentation allows the instruction RAM chip to maintain debugging accessibility while the separate key storage chip provides security verification, thus resolving the contradiction between program flexibility and data leakage prevention.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If an access key verification system is implemented to prevent data leakage, then security is improved, but device complexity increases due to additional hardware requirements

Engineering Contradiction:
Improvedata leakage preventionVSAvoidhardware complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The access key verification function is merged with the existing debugger connection interface. The debugger connection signal serves dual purposes: both establishing debugging access and triggering access key verification. This merging avoids adding separate verification hardware, thus preventing increase in device complexity while maintaining security.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If debugger connection is prohibited to prevent data leakage, then security is improved, but program development efficiency deteriorates

Engineering Contradiction:
Improvedata leakage preventionVSAvoidprogram development efficiency
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The debugger connection permission is made dynamic through the access key verification mechanism. Instead of permanently prohibiting debugger connection, the system dynamically controls access by verifying access keys in real-time. This dynamic approach allows legitimate debugging operations to proceed while blocking unauthorized access, thus maintaining both security and development efficiency.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8103923B2Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
Publication Date: 2012.01.24 RENESAS ELECTRONICS CORP
  • US8103923B2 patent drawing
  • US8103923B2 patent drawing
  • US8103923B2 patent drawing

AI summary

A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger, and the second chip includes a memory that stores a first data and the program including the first instruction group and a second instruction group, the first data is generated based on a second data inputted from the second debugger, a second processing unit that executes the second instruction group, a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger, and the first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on the second data and a third data inputted from the first debugger.