Semiconductor Debugging via Non-Test Pin Reconfiguration
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Solution Overview
Problem
Debugging semiconductor devices, such as memory devices, is challenging when the dedicated test pins are not accessible, as they are not connected to the supporting structure, making it difficult or impossible to perform debugging operations without physically removing the device from the PCB.
Innovation Solution
Utilizing non-test pins, such as the reset and clock pins, to exchange debugging information with an external debugging component by modifying their function to enable bidirectional data transfer, allowing debugging to be performed without disconnecting the device from the PCB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated test pins are used for debugging, then debugging capability is provided, but the pins are not accessible when not connected to the supporting structure
Solution Approach 1:
The patent applies multi-functionality by enabling non-test pins (such as data pins D0-D7, address pins A0-A7, control pins RD_WR, CS, RAS, CAS) to serve dual purposes: their original functional roles during normal operation and debugging communication roles when debugging mode is activated. This allows the same pins to be used for both data transfer and debugging information exchange, eliminating the need for dedicated test pins that would require physical accessibility.
Solution Approach 2:
The patent inverts the traditional debugging approach by not using dedicated test pins but instead repurposing the device's functional pins for debugging communication. Instead of having separate debugging interfaces that need physical access, the invention uses the existing operational pins to carry debugging information, effectively turning the problem of inaccessible test pins around by making the functional pins serve the debugging function.
2Ease of operation
If non-test pins are used for debugging, then debugging can be performed without removing the device from PCB, but the pins must be modified to enable bidirectional data transfer
Solution Approach 1:
The patent applies dynamics by making the pin functionality changeable or reconfigurable. The controller is configured to dynamically switch between normal operational mode and debugging mode, where the same pins exhibit different functional characteristics based on the operational state. This dynamic reconfiguration allows bidirectional data transfer capability to be activated only when needed for debugging, while maintaining the pins' original unidirectional or specialized functions during normal operation.
Solution Approach 2:
The patent changes the operational parameters of the pins by modifying their function from unidirectional data/address/control signals to bidirectional debugging communication channels. This parameter change is achieved through the controller's configuration, where the same physical pins are made to accept and transmit debugging information in both directions, effectively changing their electrical and logical characteristics without altering their physical structure or connection.
3Reliability
If dedicated debugging interface is provided, then debugging capability is enhanced, but additional pins increase device complexity
Solution Approach 1:
The patent eliminates the need for additional dedicated debugging pins by making the existing pins universal. The same data pins, address pins, and control pins are used for both normal device operation and debugging communication. This multi-functionality approach maintains full debugging capability while avoiding any increase in the total number of pins or device complexity.
Solution Approach 2:
The patent merges the debugging communication function with the normal operational functions by using the same pins for both purposes. Instead of having separate debugging interfaces, the invention combines the data bus, address bus, and control signals into a unified communication channel that can carry both operational data and debugging information, thereby reducing the overall pin count while maintaining comprehensive debugging capability.
Data Source
AI summary
Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die.